Question: Explain the intel Pentium processor pipelining and superscalar architecture Or Explain the superscalar architecture

Mumbai University > Electronics and Telecommunication > Sem 4 > Microprocessor and peripherals

mumbai university mpa • 782 views
modified 4 months ago by gravatar for Abhishek Tiwari Abhishek Tiwari50 written 7 months ago by gravatar for kazi.tahoor kazi.tahoor0

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  1. It is a 32 bit microprocessor.

  2. It has 32 bit address bus and 64 bit data bus.

  3. It has internal dedicated 8 KB code cache and 8 KB data cache.

  4. It has on chip ( floating point unit) FPU.

  5. It has on chip BPL ( Branch prediction logic).

  6. It has built in sey test (BIST).

  7. It has five stage pipelining.

Decode 1 stage –

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  1. Checking for pair ability of instructions: If the instructions are pairable then instructions will move in together i.e. if an instruction takes more time in a particular stage the will wait in corresponding stage.

    If the instructions are not pairable, the instruction in V pipeline is deleted an the prefetcher will shift that instruction into the D stage of U pipeline when the earlier moves to D stage of U pipeline.

  2. Branch prediction: If either instruction is branch instruction. The branch prediction logic will predict whether the branch takes place or not.

    Integer pipeline stage of Pentium:

    a) Pre-fetch

    b) Decode 1

    c) Decode 2

    d) Execute

    e) Write back

a) Prefetch stage: It consists of a prefetcher and pre-fetch queue A and B each of 64.The prefetcher receives the line of code from code cache and store it into the active prefetch queue only one queue is active at a time. The current queue remains active until branch prediction logic has predicted that branch will not be taken. When the branch is predicted to be taken, the prefetcher switches to another queue and store it in another queue.

If the branch is taken then the instruction in queue are valid and execution until does not start.

If the branch is not taken the prefetch queue and pipeline are flushed, and prefetcher switches back to 1st queue which supplies instruction that were fetched prior to branch predicted. The flush and the switch cause the execution until to start for 3 – 4 clocks. If the branch is predicted to be taken then the BPL will indicate it to prefetcher.

b) Decode 1: instructors are decoded into the Pentium’s internal instruction format. Branch prediction also takes place at this stage.

c) Decode 2 stage:

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The basic function of Decode 2 stage is:

  1. Address calculation for the operand residing memory for U-pipeline as well as V-pipeline.

  2. It performs segmentation level protection check required when processor is forming the memory address.

These both functions are supported by segmentation unit.

d) Execution stage: The EU comprises for ALU for U – Pipeline with barrel shifter and V-pipeline. The data access from RAM is processed by this stage. Both instructions enter this stage simultaneously.

modified 5 months ago by gravatar for Ankit Pandey Ankit Pandey70 written 5 months ago by gravatar for RB RB ♦♦ 110
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