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With the help of suitable diagram, justify True or False: Cascode current mirror current matching performance is better than Basic current mirror.

Subject: CMOS VLSI Design

Topic: CMOS analog building blocks

Difficulty: Difficult

cvd • 707  views
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• A current mirror is a circuit block which functions to produce a copy of the current flowing into or out of an input terminal by replicating the current in an output terminal.
• An important feature of the current mirror is a relatively high output resistance which helps to keep the output current constant regardless of load conditions.
• Another feature of the current mirror is a relatively low input resistance which helps to keep the input current constant regardless of drive conditions.
• The current being 'copied' can be, and often is, a varying signal current. The current mirror is often used to provide bias currents and active loads in amplifier stages.

• The simple current mirror can, obviously, also be implemented using MOSFET transistors, as shown in figure. From above figure, IREF is drain current of M1. Therefore IREF can be given as,

• Note that, here we have neglected channel length modulation effect. Similarly, Iout can be given by,

............... [From (1) and (2)]

• Thus by precisely adjusting values of (W/L) ratios of both the transistors, we can get the required value of output current.

Drawback of Basic current mirror:

• In the analysis of basic current mirrors, we have neglected channel length modulation. The channel length modulation effect results in significant error in copying currents.
• For basic current mirror, we can modify the equations by considering channel length modulation. We can write,

• While VDS1 = VGS1 = VGS2, VDS2 ≠ VGS2 (because of the circuitry fed by M2.)

• In order to suppress the effect of channel length modulation, a cascode current mirror can be used.

Cascode current mirror: - As shown in figure below, one more transistor M3 is added. In the circuit of basic current mirror and Vb is chosen such that Vx = Vy, then Iout closely tracks IREF.

• Now, to generate Vb in above circuit,

• The objective is to ensure Vx = Vy, ∴ Vb – VGS3 = Vx or Vb = VGS3 + Vx.

• This result suggests that if a gate source voltage is added to Vx, to obtain required value of Vb.
• As shown in figure b, the idea is to place another diode connected device M0, in series with M1 and thereby generating a voltage VN = VGS0 + Vx.
• The proper choice of the dimensions of M0 with respect to those of M3 yields VGS0 = VGS3. Thus if

then VGS3 = VGS0 and Vx = Vy.