Assuming

Circuit to be designed:

M3 and M4 are the diode connected loads. M8 is missing and can be added later for offset nulling.

For good stability,
|$P_1$| > |$P_2$|

Further we can see that Z1 > 10 GBW

From (1) and (2) we get,

$C_C$ ≥ 0.22 $C_2$

This is the required condition for stability.

The total load capacitance as given to us
$C_L$ = $C_2$ = 10pF

$C_C$ ≥ 0.22 pF

Choose $C_C$ = 3 pF or 2.5 pF

Given slew rate

ICMR Evaluation:

If the maximum VT variation due to body bias is assumed to be 0.15 V

Taking Vin,max and Vin,min values

Evaluation of (W/L)1 and (W/L)2

Evaluation of (W/L) 5:
ICMR is given is -1.25 to 2V

Evaluation of (W/L) 6
From phase margin 8 zero place chosen by us (∅_n 8 Z1 )
We have obtained

Differentiating above equation w. r. t. (1+λ.VGS6)

This value of IDS6 is very high and will consume high power dissipation. (Typically IDS6 should be less than 100)

- However (W/L)6 can also be found through gm6 & gm4 relationship.
M4 and M6 are mirror configuration almost.

Evaluation of M7
Since M5 & M6 are current mirror configuration & using
I6 = I7 we get,

Since M5 & M9 – M12 are in mirror configuration and we can assume

Verification of DC gain