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List the non-ideal effects in charge pump circuit and justify how it impacts the PLL performance.

Subject: CMOS VLSI Design

Topic: Mixed Signal Circuits

Difficulty: Medium

cvd • 723  views
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#### A) Phase frequency detector (PFD)/ Charge pump (CP) non-linearity:

• Several imperfections on the PFD/ CP circuits lead to high ripple on the control voltage even when the loop is locked. Therefore ripple modulates the VCO frequency producing a waveform which is no longer periodic. • The PFD implementation on above circuit (Fig. a) generates narrow coincident pulses on both $Q_A$ and $Q_B$ even when the input phase difference is zero.

• A and B rise simultaneously, so does $Q_A$ and $Q_B$. Therefore reset activates. (Fig. b) • Even when PLL is locked, $Q_A$ and $Q_B$ simultaneously turn ON the charge pump for a finite period & $T_p$ = 10 $T_D$, where $T_D$ denotes the gate delay.

#### B) Jitter in PLL:

• The response of phase-locked loops to jitter is of extreme importance in most applications.
• As shown in Fig. c, a strictly periodic waveform, x1 (t), contains zero crossings that are evenly spaced in time. Now consider the nearly periodic signal x2(t), whose period experiences small changes, deviating the zero crossings from their ideal points. We say the latter waveform suffers from jitter.
• Plotting the total phase, Φtot, and the excess phase, Φex, of the two waveforms, it is observed that jitter manifests itself as variation of the excess phase with time. Ignoring the harmonics above the fundamental, we can write where, Φn models the variation of the period. • The rate at which the jitter varies is also important. Consider the two jittery waveforms depicted in Fig. d. The first signal, y1(t), experiences "slow jitter" because its instantaneous frequency varies slowly from one period to the next. The second signal, y2(t), experiences “fast jitter”.

• The rate of change is also evident from the excess phase plots of the two waveforms. 