Mumbai University > Electronics Engineering > Sem 6 > Embedded System and RTOS
As the complexity of hardware increases, the number of chips present in board and interconnection among them may also increase. The device package in PCB becomes miniature to reduce total board space occupied by them and multiple layers of PCB are required to route the interconnection.
i) Miniaturization makes it difficult to debug the hardware using magnifying glass, multimeter, etc to check the interconnection among various chips.
ii) Boundary scan is a technique used for testing the interconnection among various chips, which support JTAG interface.
iii) JTAG port contains five signal lines viz. TDI, TDO, TCK, TRST and TMS, which together forms Test Access Port (TAP). Each device will have its own TAP.
iv) A boundary scan path is formed inside the board by interconnecting the device through JTAG signal lines.
v) The TDI pin of TAP of PCB is connected to the TDI pin of the first device. TDO pin off the first device is connected to TDI pin of second device. Same way all devices are interconnected. TDO of the last JTAG device is connected to TDO pin of TAP of PCB.
vi) TCK and TMS line of the devices are connected to clock and test mode select line of TAP of PCB. This forms a boundary scan path.
vii) The boundary scan cell is the multipurpose memory cell.
viii) The boundary scan cell associated with the input pins of an IC is known as input cells. The boundary scan cell associated with the output pins of an IC is known as output cells.
ix) The boundary scan cells can be used to capture input pin signal state and pass to internal circuitry capturing the signals from the internal circuitry and passing it to the output pin and shifting the data received from TDI of TAP.
x) The boundary scan cells can be operated in following modes –
Normal mode: The input of the boundary scan cell appears directly at its output.
Capture mode: In Capture mode, the boundary scan cell associated with each input pin of the chip captures the signal from respective pins to the cell and boundary scan cell associated with each output pin captures the signal from internal circuitry.
Update mode: In the Update mode, boundary scan cell associated with each input pin of chip passes the already captured data to the internal circuitry and boundary scan cell associated with each output pin of chip passes captured data to output pin.
Shift mode: In Shift mode, data is shifted from TDI pin to TDO pin off the device through boundary scan cells.
xi) ICs supporting boundary scan contain additional registers.
Instruction register: Holds and processes the instructions received over TAP.
Bypass register: Used for bypassing the boundary scan path of device and directly introducing TDI pin to TDO pin.
xii) RUN BIST is the instruction used for performing self-test on internal functioning of the chip.