Page: Explain SRAM in detail
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The data storage cell, i.e., the 1-bit memory cell in static RAM arrays, invariably consists of a simple latch circuit with two stable operating points (states). Depending on the preserved state of the two-inverter latch circuit, the data being held in the memory cell will be interpreted either as a logic "0" or as a logic " 1." To access (read and write) the data contained in the memory cell via the bit line, we need at least one switch, which iscontrolled by the corresponding word line, i.e., the row address selection signal.

Operation and Design Strategy

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Figure shows a typical four-transistor resistive-load SRAM cell widely used in high-density memory arrays, consisting of a pair of cross-coupled inverters. The two stable operating points of this basic latch circuit are used to store a one-bit piece of information; hence, this pair of cross-coupled inverters make up the central component of the SRAM cell. To perform read and write operations, we use two nMOS pass transistors, both of which are driven by the row select signal, RS. Note that the SRAM cell shown in Fig is accessed via two bit lines or columns, instead of one. This complementary column arrangement allows for a more reliable operation.

When the word line (RS) is not selected, i.e., when the voltage level of line RS is equal to logic "0," the pass transistors M3 and M4 are turned off. The simple latch circuit consisting of two cross-connected inverters preserves one of its two stable operating points; hence, data is being held. At this point, consider the two columns, $C$ and $\bar C$. If all word lines in the SRAM array are inactive,the relatively large column capacitances arecharged-up by the column pull-up transistors, MP1 and MP2. Since both transistors operate in saturation, the steady-state voltage level Vc for both columns is determined by the following relationship: $V_{DD} -V_C = V_{To} + \gamma (\sqrt{|2\phi_F| + V_C} - \sqrt{|2\phi_F|})$ Assuming $V_{DD}$ = 5 V, $V_{To}$ = 1 V, $|2\phi_F| $ = 0.6 V, and $\gamma $= 0.4 $V^{1/2}$, this voltage level is found to be approximately equal to 3.5 V. Note that the voltage levels of the two complementary bit lines (columns) are equal during this phase. Read and Write Operations Now assume that we select the memory cell by raising its word line voltage to logic "1," hence, the pass transistors M3 and M4 are turned on. Once the memory cell is selected, four basic operations may be performed on this cell. a) Write "1" operation: The voltage level of column $\bar C$ is forced to logic-low by the data-write circuitry. The driver transistor M1 turns off. The voltage $V_1$ attains a logic-high level, while $V_2$ goes low. b) Read "1" operation: The voltage of column C retains its precharge level while the voltage of column $\bar C$ is pulled down by M2 and M4. The data-read circuitry detects the small voltage difference ($V_C > V_{\bar C}$) and amplifies it as a logic "1" data output. c) Write "0" operation: The voltage level of column C is forced to logic-low by the data-write circuitry. The driver transistor M2 turns off. The voltage V2 attains a logic-high level, while V1 goes low. d) Read "0" operation: The voltage of column $\bar C$ retains its precharge level while the voltage of column C is pulled down by M1 and M3. The data-read circuitry detects the small voltage difference ($V_C < V_{\bar C}$) and amplifies it as a logic "0" data output.

Typical voltage waveforms associated with the word line RS and the two pseudo-complementary bit lines are shown qualitatively in Fig. Note that the voltage difference between the two columns during a read operation may be only a few hundred millivolts, which must be detected by the data-read circuitry. The reason for this is that the two nMOS transistors in series (e.g., MI and M3 for read "0") pulling down the column during the read phase cannot discharge the large column capacitance quickly.

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modified 4 days ago  • written 4 days ago by gravatar for Vedant Chikhale Vedant Chikhale0
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