**1 Answer**

written 5.7 years ago by |

A CMOS NOR2 gate can be built by using two complementary pairs as shown in Figure. Input A is connected to MnA and MpA, while B controls MnB and MpB. Note that the nFETs are connected in parallel, while the pFETs form a series chain. To understand the operation of the gate, we examine the conduction states of the transistors for different input voltages $V_{in,A}$ and $V_{in,B}. $ If $V_{in,A} = V_{DD}$, then MnA is ON and MpA is OFF; since MnA provides a conducting path from the ground to the output, $V_{out} = 0V.$ Setting $V_{in,B} = V_{DD}$ turns MnB ON and MpB OFF and also results in $V_{out} = 0V.$ And, if both $V_{in,A}$ and $V_{in,B} are high, then both nFETs are ON and the output voltage is $V_{out} = 0V.$ The only input combination that results in $V_{out} = V_{DD}$ is when $V_{in,A} = 0 V = $V_{in,B}, $ since both pFETs are ON while both nFETs are OFF. As verified by the truth table in Figure, this gives exactly the NOR2 operation.

We may also verify the logic function by viewing the circuit as a simple multiplexor between the power supply $V_{DD}$ (“1”) and ground ( “0”) as shown in Figure. Using the logic equations for MOSFETs gives the output as

$g = \bar A . \bar B . 1 + (A +B) . 0$

As in the case of the NAND gate, the nFET terms logically evaluate to 0 which leaves

$g = \bar A . \bar B = \bar {A +B} $

using the DeMorgan theorem. This verifies our previous statement that the logic function is determined entirely by the topology of the circuit.