written 5.8 years ago by |
Q. Give the methods to meet Design challenges.
) Clock Rate Reduction:
2.3 uW of power decreases per 100 kHz of decreased clockrate.
Therefore, when clock rate decreases from 8000 kHz to 100 kHz, then power dissipation is decreased by 200 uW, which is nearly similar to when clock is non fuctional.
ii) Voltage reduction:
In portable devices such as cellular phone, which is a CMOS circuit, power dissipation decreases by one sixth. Therefore, time interval needed for recharging the battery increases by factor of 6.
iii) Process deadlines:
It is a challenge to meet the deadlines of all processes in the system while keeping the memory, power dissipation, processor, clock rate and cost at minimum.
iv) Flexibility and Upgrade availability:
In design while keeping the cost minimum and without significant engineering cost is a challenge.
v) Reliability:
Designing a reliable product by appropriate design testing and thorough verification is a challenge.
Testing -- to find errors and validate that implemented software is as per the specifications.
Verification -- to ensure that specific function are correctly implemented.
Validation -- to ensure that a system has been created as per requirements.