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Module 2 : Unit 2
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1) Resistive load

2) Saturated load (Enhancement type nmos)

3) Linear load enhancement

4) Depletion load

5) Pseudo nmos

6) CMOS Inverter

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2) Enhancement Saturated load 3) Enhancement Linear Load
2) $V_{GS load}$ Load = $V_{DS}$ load but always in saturation. Advantage i) Single power supply ii) Relatively simple fabrication process 3) Disadvantage : -i) 2 power are reg. ii) Highly standby power dissipation iii) Body bias effect iv) More chip due to extra power supply & connectivity
Disadvatgaes Advantages
i) When $V_{DL} = V_{out}$, current flows directly from $V_{DD}$ to gnd $V_{OH} = V_{DD}$ high noise margin than sat load is expected
2) $V_{OH} = V_{DD} - V_{Tload}$, $V_{DD} - V_{TL}$ may be so small to accept at high i/p $V_{GG} \gt V_{DD} + V_{TL} (V_{DD})$

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4) Depletion Load :

$V_{GS} \gt V_{DS} + V_T$ in linear

$V_{DS} \lt V_{GS} - V_T$

$V_{GS} \gt V_{DS} + V_T$

$V_{DS} \lt V_{GS} - V_T$

4) $V_{in} V_{out}$ Driver load,

$V_{OL} V_{OH}$ cutoff linear

$V_{IL} = V_{OH}$ sat linear

$V_{IH}$ small Linear sat

$V_{OH}$ $V_{OL}$ linear saturation

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ADV: 1) Sharp VTC transition & better noise margin.

2) Single power supply

3) Small overall layout area.

Disadv: Fabrication of dept slightly more complicated and requires additional processing steps

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CMOS Inverter (Explain VTC)

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1) Find out $V_{IL}$

$I_L = I_D$

When $V_{IN} = V_{IL}$, nMOS - Sat

pMOS - Linear

n, $I_D = \frac{kn}{2}[V_{gsn} - V_{Tn}]^2 = \frac{kn}{2}[V_{in} - V_{th}]^2$

p, $I_L = \frac{kn}{2}[2(V_{gsp} - V_{Tp})V_{dsp} - V_{ds^2p}^2] = \frac{kn}{2}[2(V_{in} - V_{DD}-V_{TP})(V_{out} - V_{DD})-(V_{out} - V_{DD})^2]$

$I_D = I_L$

Diff wrt $V_{in}$ and substitute

$V_{in} = V_{IL} And \frac{dV_{out}}{dV_{in}} = 1$

$V_{IL} = 2V_{out} + V_{TP} - \frac{V_{DD}}{1 + K_R} + K_R V_{TH}$

2) Find out $V_{IH}$

$V_{IH} = V_{IH}$

At $V_{IH}$, nmos - linear

pmos - sat

$kn[2(V_{in} - V_{TO})V_{out} - V_{out}^2] = kp(V_{in} - V_{DD} - V_{Tp})^2$

dwrt $V_{in}$ and substitute

$kn[2(V_{in} - V_{TO})\frac{dV_{out}}{dV_{in}} + 2V_{out}(1) - (-1)2V_{out}]$

$V_{IH} = KR\frac{(2V_{out} + V_{Th}) + V_{DD} + V_{TP}}{1 + K_R}$

3) Find out $V_{OH}$

i.e. When $V_{in} = 0V$ $V_{out} = V_{OH}$

When $V_{in} = 0V$ $V_{gsd} \lt V_{Th}$

nmos is in cutoff

pmos is in linear

=> $V_{OH} = V_{DD}$

4) Find out $V_{OL}$

When, $V_{in} = V_{DD}$

nmos -> conducting -> linear

pmos -> cutoff

=> $V_{OL} = 0V$

Advantages:

i) Static power dissipation is zero

ii) Sharp VTC & NM

iii) High Input impedence

iv) low Output impedence

Disadvantages:

i) Fabrication steps are enhanced

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