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Domino logic is a system design style that eliminates the nMOS-nMOS glitch problem without introducing pMOS-type logic stages. The basis for domino circuits arises from once again studying the origin of the glitch problem in the nMOS-nMOS cascade.

Consider the basic domino logic circuit shown in Figure. This consists of a dynamic nMOS gate with the output cascaded into a static inverter. The output of the domino gate is taken to be at the output of the inverter, which is directly connected to the input nFET Min of the next stage. Without the inverter, capacitor $C_X$ is precharged to $V_{DD}$ which would turn on Min . However, with the inverter added as shown, a precharge event $\phi = 0$ allows the capacitor $C_X$ to precharge to a voltage of

$V_X \rightarrow V_{DD}$

which then gives

$V_{out} \rightarrow 0 $

at the output of the inverter. This drives the nFET Min into cutoff, eliminating the possibility of a glitch in the next stage. Cascading domino stages thus allows for all nFET glitch-free logic.

Domino logic circuits do have several characteristics that complicates their use. One is due to the fact that the inverter complements the output of the dynamic nMOS gate. Consider the evaluate circuit shown in Figure where we assume that the precharge has already established voltages of $V_X = V_{DD}$ and $V_{out} = 0v$ on $C_X $ and $C_{out}$ respectively. Let us direct our interest to the internal node variable X and examine the circuit when a discharge takes place. To discharge $C_X$ the nFET logic array must act as a closed switch.

This in turn requires that at least some of the inputs x, y, z are at logic 1 values to turn on the required transistors; the actual combination depends upon the logic function. When $C_X$ discharges, $V_X \rightarrow 0v$ corresponding to $X \rightarrow 0$ .The output of the dynamic logic stage is X so we see that the interior dynamic nMOS circuit automatically provides the NOT operation: logic 1’s at the input give a value of X = 0. However, in the domino configuration, the internal node X is not the output. Instead, the output of the gate is taken after the inverter, and

$f = \bar X$

A discharge of $C_X$ thus results in an output of f=1, illustrating the fact that domino logic is noninverting. This means, for example, that we can create gates for the basic AND and OR operations, but cannot implement the NOT function. The only way to obtain the NOT is to add another inverter to the output, but this takes us back to the glitch problem.

From the viewpoint of logic design, this can be tricky to deal with since the NOT operation is required to form a complete logic set.3 This characteristic can make domino logic designs somewhat tricky. We must provide the NOT operation somewhere, but it cannot be placed within the chain. The solution is to restrict inverters to the beginning or end of a domino chain.

Figure shows an OR3 gate as an example of a domino logic gate. Precharge takes place when $\phi = 0$ with $C_X$ charging to a voltage of $V_X = V_{DD}$. If any one or more of the inputs x, y, or z is at a logic 1 level when $\phi = 1, C_X$, discharges and $V_X \rightarrow 0v$. This forces the output voltage to change from the precharge value of 0v to a final value of $V_{out} = V_{DD} $ which is interpreted as a logic 1 output. Thus, we see that

g = x + y + z

describes the operation as stated. Another example of a domino gate is drawn in Figure. Using the same arguments gives

f = x.y + z

which is in AO (AND-OR) form. OA and other functions can be created in the same manner.