Design Styles:

1. Static CMOS Design

For a given boolean function F follow following steps:

i) Compliment F i.e $F^{-}$ and implement PU i.e. nMOS network.

ii) $F^{-}|_{dual}$ => Take that dual of complimented function & implement p network.

iii) Determine transistor sizing.

Refer equivalent cKt of NAND & NOR

Q. i) $F = (AB + CD)^{-}$

ii) $F = ((A + B + C)(D + E)G)^{-}$

iii) $Y = (A + BC + BD)^{-}$

Sol.

i $F = (AB + CD)^{-}$

=> $F^{-} = (AB + CD)$

=> $F^{-}|_{dual} = (A + B).(C + D)$

ii $F = ((A + B + C)(D + E)G)^{-}$

=> $F^{-} = (A + B + C)(D + E)G$

=> $F^{-}|_{dual} = (ABC) + (DE) + G$

iii $Y = (A + BC + BD)^{-}$

=> $Y^{-} = A + BC + BD$

=> $F^{-}|_{dual} = A.(CD + B)$