Design Styles:

1. Static CMOS Design:

Q Implement 2 : 1 MUX using transmission gate.

Q 4 : 1 MUX

• Implement:

$F = AB + AB^{-}C + A^{-}C$ Using transmission

Design Styles:-

$F = (A.B)^{-}$

$F^{-} = A.B$ (PDN) Series

$F^{-}|_{dual} = A + B$ (PUN) parallel

Series : $(W/L)_{eq} = \frac{1}{\Sigma_{eq}1/(W/L)_K}$

Parallel : $(W/L)_{eq} = \Sigma_{eq}(W/L)_K$

adv : Very less power dissipation , Better noise margin

1. Dynamic cKt:

disadv charge sharing, charge leakage, Race(cascading problem).

1. Domino logic:

4 : 1 MUX

SR latch