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Module 4 : Unit 2
written 7.1 years ago by gravatar for teamques10 teamques10 ★ 70k
vlsi design
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written 7.1 years ago by gravatar for teamques10 teamques10 ★ 70k

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It memory cell (DRAM)

  • Write

-1. Drive bit line

-2. Select Rou

  • Read

  1. precharge bit line to $V_{dd}/2$.

  2. Select row

  3. Cell and bit line share charges - Minute voltage change on BL

  4. Sense (fancy sense amp.).Can detect changes of 1 million eelectrons

  5. Write: restore the valve

Refresh

  1. Just to do …

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