It memory cell (DRAM)

• Write

-1. Drive bit line

-2. Select Rou

• Read

1. precharge bit line to $V_{dd}/2$.

2. Select row

3. Cell and bit line share charges - Minute voltage change on BL

4. Sense (fancy sense amp.).Can detect changes of 1 million eelectrons

5. Write: restore the valve

Refresh

1. Just to do dummy read to every ccel

3 - T DRAM cell with the pull-up and read/unite circuity

RD/WR Access

DRAM operation mode

1. Async mode – uses RAS and CAS

2. sync mode

leakage current

1. $I_{sub}$ – through cell access transfer

2. $I_j$—junctionleakage current at storage

3. $I_{cell}$ to cell tunneling I three thin dieletric $T_{OX}$

4. $I_{tunnelling}$ $I_{leakage}$ accross the field oxide

6T SRAM

Read operation.

1.Assume logic“0” started at the left side and logic “1” at the right.

2.M2 -M5 =OFF and M1 M6 =On (linear)

3.V1=0 v and V2= Vod before M3&M4 are ON

1. DL—Precharged to Vdd

2. row selection line = low in stand by raised to Vo

3. M3- M4= on mem cell connected to dL

4. M4—D & S (same potential) no current voltage is maintained.

5. M3- M1 conducts current flow M3—M1—G cap discharges slowly voltage lecel of col C drops slightly.

6. Voltage diff is developed at 0 l sense amplifier is ON diff in C and C is fed to sense ap to generate a valid low 0/10 – stored in data buffer

7. upon completion – WL = 0

WRITE OPERATION

1. Assume logic “1” is started

2. M1-M6 = off and M5- M2 = on (linear)

3. V1= Vdd and V2 = ov before M3 M4 are ON

4. Row sdetion line–low in stand by – raised to VDd

5. M3- M4 = on Mem cell are connected to dataliareTo change stored info that is to forveV1 =0V and V2=VDd , the V1 node voltage must be reduced below VTh of M2 so that M2 turn off firs

6. The M2 – forced in cutoff mode during write “0” operation. Subsequently M1 turn on changing the stored info