Question: Write VHDL code for 3:8 decoder with active low truth table
0
X(2) X(1) X(0) Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7)
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0

Entity decoder is port ( x : in std_logic_vector (2 down too)

Y : out std_logic_vector ( 0 down to 7 )

en : in std_logic) ;

End decoders;

Architecture behavioral of decoder is signal Y 1 : std_logic_vector (7 down to 0) ;

Begin Y1 < = “0111 111” when z = “ 000 “ else

“10111111” when x = “001” else

“11011111” when x = “010” else

“11101111” when x = 011” else

“11110111” when x = “100” else

“11111011” when x = “101” else

“11111101” when x = “110” else

“11111110” when x = “111” else

“11111111” when others;

Y < = y, when en = ‘0’ else “1111 1111” ;

End behavioral.

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renu • 125 views
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modified 4 weeks ago  • written 6 months ago by gravatar for RB RB ♦♦ 110
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