Question: comparison of TTL and CMOS
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Parameters TTL CMOS
1] Design. It is designed using BJTs. It is designed using FETs.
2] Density of logic gates. It has greater density of logic gates since a logic gate consists of BJTs and extra components. It is designed using FETs. it has lesser density of logic gates since a logic gate consists of two FETs.
3] Power. 10MW per gate 10 nW per gate
4] Cost. It is relatively cheaper. It is expensive.
5] Damage due to electrostatic charge. It is relatively cheaper, less susceptible It is expensive, more susceptible to damage.
6] Power consumption. Consumes more power at rest. Consumes less power at rest.
7] Propagation delay. 10ns 25ns-50ns.
8] Voltage level range. 0 to VDD, low level is 0 to 1/3 VOD and high level is 2/3 VDD to VDD. 0 to VCC where VCC is 4.75 - 5.25 V, 0 - 0.8 V creates logic level 0 & 2v - vcc creates logic 1.
9] Fan-out. 10 50
10]] Fan-in. 12-14 Greater than 10
11] Basic gates used. NAND gates NAND -NOR gates.
12] Noise margin. 0.5V 1.5V
13] Noise immunity. Worse than CMOS Better than TTL
renu • 43 views
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written 10 weeks ago by gravatar for RB RB ♦♦ 100
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