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Entity declaration in VHDL for NOR gate.
written 4.9 years ago by | modified 2.3 years ago by |
a] Entity declaration in VHDL for NOR gate.
NOR gate
Library JEEE;
use JEEE, STD_LOGIC_1164.ALL;
entity nor-top is
Port (A . in STD_LOGIC; - - - - - NOR gate input
B : in STD_LOGIC; NOR gate input
Y : Out STD_LOGIC; ) NOR gate output
end _ nor_top;
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