Entity declaration in VHDL for NOR gate.

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Entity declaration in VHDL for NOR gate.

written 5.8 years ago by

teamques10 ★ 69k

modified 3.2 years ago by

Krishna_Agrawal • 2.7k

a] Entity declaration in VHDL for NOR gate.

NOR gate

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Library JEEE;

use JEEE, STD_LOGIC_1164.ALL;

entity nor-top is

Port (A . in STD_LOGIC; - - - - - NOR gate input

B : in STD_LOGIC; NOR gate input

Y : Out STD_LOGIC; ) NOR gate output

end _ nor_top;

b] BCD Addition:

enter image description here

digital logic design

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