Rate around condition:
The difficulty of both i/ps S = R = 1 is not allowed in SR flip-flops is eliminated in IK f/E by using feedback connection by o/p to i/p of gates $G_3$ and $G_4$
Assume that i/p to $G_3$ & $G_4$ which are coming from feedback do not change during one active high clock pulse which is not true because of feedback connection.
Now assume c/k = j = k = 1 & $Q_n = 0$ & $Q_n = 1$
After at time interval $\triangle$T (propagation delay) through two NAND gates which are in series output will change to logic 1 after another time interval $\triangle$ T & this process continues hence we conclude that for TH of pulse that o/p will oscillates between logic 0 and logic 1.
At the end of C/H pulse the value of new o/p is unpredictable this situation is referred to race around condition.
To overcome this we use master slave J.K F/F.
Master slave JK f/f:
A master slave J/K F/F is called e connection of one JK and 1 SR f/f with feedback connection from o/p of 2nd stage to i/p of 1st stage.
Positive c/h pulse is applied to the first f/f and it is inverted before applying to 2nd f/f when c/n = 1 1st f/f is enabled and 2nd disabled and vice versa.
The 2nd f/f simply follows the o/p of 1st f/f hence it is referred as slave and 1st as master hence entire configuration is now as master slave. JK
In this cnt input to mns and mG4 do not change during the active high clock pulse hence o/p remains constant for one c/n pulse, hence rate around condition does not exist.