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Digital Electronics And Logic Design Question Paper - Dec 18 - Information Technology (Semester 3) - Pune University (PU)
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Digital Electronics And Logic Design - Dec 18
Information Technology (Semester 3)
Total marks: 50
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt question nos. 1 or 2, 3 or 4, 5 or 6, 7 or 8.
(3) Draw neat diagrams wherever necessary.
1.a.
Compare TTL and CMOS logic families.
(6 marks)
00
1.b.
Minimize the given Boolean expression using Quine-McCuskey method :
(6 marks)
00
F(A, B, C, D) = 
(0, 1, 3, 7, 8, 9, 11, 15).
OR
2.a.
Convert the following numbers in Binary form :
(5 marks)
00
i. $(125.12)_{10}=(?)_{2}$
ii. $(337.025)_{8}=(?)_{2}$
iii. $(5 \mathrm{DB} \cdot \mathrm{FA})_{16}=(?)_{2}$
2.b.
Implement given function using 8 : 1 MUX and logic gates.
(5 marks)
00
F(A, B, C, D) = (0, 1, 3, 4, 8, 9, 15).
3.a.
Design and implement T flip-flop using SR flip-flop.
(6 marks)
00
3.b.
Draw state diagram to detect sequence 101 using Moore Modeling and Mealy modeling style.
(6 marks)
00
OR
4.a.
Give comparison of Combinational circuit with Sequential circuit. Draw and explain one-bit memory cell using NAND gates.
(6 marks)
00
4.b.
Design sequence generator to generate sequence 1010 using shift register.
(6 marks)
00
5.a.
Design and implement given functions F1 and F2 using suitable PAL :
(7 marks)
00
F1(A, B, C) = (0, 1, 3, 6, 7);
F2(A, B, C) = (1, 2, 4, 6)
5.b.
Write the comparison of FPGA and CPLD.
(5 marks)
00
OR
6.a.
Draw and explain various components used in ASM chart.
(6 marks)
00
6.b.
Implement Full adder circuit using suitable PLA.
(7 marks)
00
7.a.
Explain data objects used in VHDL with appropriate examples.
(6 marks)
00
7.b.
Write VHDL code (Entity and Architecture) for Full adder using Behavioural modeling style.
(7 marks)
00
OR
8.a.
Explain difference between Sequential statements and Concurrent statements used in VHDL with suitable examples.
(6 marks)
00
8.b.
Write VHDL code for half-adder using structural modeling style.
(7 marks)
00
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