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Digital Electronics And Logic Design Question Paper - Jun 18 - Information Technology (Semester 3) - Pune University (PU)
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Digital Electronics And Logic Design - Jun 18
Information Technology (Semester 3)
Total marks: 50
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Answer Q. Nos. 1 or 2, 3 or 4, 5 or 6 and 7 6 or 8.
(3) Draw neat diagrams wherever necessary.
1.a.
Do the following
(6 marks)
00
i. $(27.50) 2-(68.75) 2$ Using 2's compliment method.
ii. Convert the decimal number 25 into Binary format, Excess-3 format and BCD format
1.b.
Design Full subtractor circuit using decoder IC 74138.
(6 marks)
00
OR
2.a.
Define following terms related to logic families
(6 marks)
00
i. Power dissipation
ii. Fan-in
iii. Fan-out
iv. Noise margin
v. Propagation delay
vi. Figure of merit
2.b.
Draw and explain 4 bit BCD adder using IC 7483.
(6 marks)
00
3.a.
Compare Asynchronous counter with Synchronous counter. Design MOD 11 $\mathrm{up}$ counter using IC 74191.
(6 marks)
00
3.b.
Draw and explain 4 bit Ring counter . Write the Truth Table for same showing all possible states if initial state is 1100.
(6 marks)
00
OR
4.a.
Design and draw MOD 56 counter using IC 7490 and explain its operation.
(6 marks)
00
4.b.
Draw and explain 4 bit SISO and SIPO shift register. Give application of each.
(6 marks)
00
5.a.
Draw ASM chart for 2 bit binary up counter with mode control input M such that
(7 marks)
00
For M = 1 Counter counts up
For M = 0 Counter holds preset state.
Design the circuit using multiplexer controller method.
5.b.
Design 4:1 multiplexer using suitable PAL.
(6 marks)
00
OR
6.a.
Design 3 bit Binary to Gray code converter using suitable PLA.
(7 marks)
00
6.b.
Draw and explain Internal Architecture of CPLD in detail.
(6 marks)
00
7.a.
What is VHDL? Explain components of VHDL in detail with example of 2 input AND gate.
(6 marks)
00
7.b.
Write VHDL code (Entity and Architecture) for 4:1 Multiplexer using data flow modeling method.
(7 marks)
00
OR
8.a.
Compare sequential and concurrent statements in VHDL with suitable example.
(6 marks)
00
8.b.
Write VHDL code(Entity and Architecture) in behaviour modeling style for 2 bit synchronous up/down counter. Consider
(7 marks)
00
Mode = 0 Up counting
Mode = 1 Down counting
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