Information Technology (Semester 3)
Total marks: 50
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt Question nos 1 or 2, 3 or 4, 5 or 6, 7 or 8.
(3) Draw neat diagrams wherever necessary.
1.a.
Explain any 3 characteristics of Digital ICs.
(6 marks)
00
1.b.
Implement the following Boolean function using single 8:1 multiplexer :
$\mathrm{F}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\Sigma \mathrm{m}(1,4,6,9,13)$
(6 marks)
00
OR
2.a.
Do the following :
i. $(7 \mathrm{F})_{16}-(5 \mathrm{C})_{16}$ using 2's complement method
ii. $(735.25)_{10}=(?)_{16}$
iii. $(101011.111011)_{2}=(?)_{8}(?)_{16}$
(6 marks)
00
2.b.
Simplify the following Boolean function using Quine MC-Clusky Technique $\mathrm{F}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\mathfrak{L}\left(0,1_{2}, 3,7,8,9,11,15\right)$
(6 marks)
00
3.a.
Design and draw logic diagram of mod 45 counter using IC 7490.
(6 marks)
00
3.b.
Design sequence generator to generate the sequence 1011 using shift register IC 74194.
(6 marks)
00
OR
4.a.
Explain with a neat diagram Ring counter.
(6 marks)
00
4.b.
Design flip-flop conversion logic to convert JK flip-flop to T flip-flop.
(6 marks)
00
5.a.
Draw the ASM chart for 2 bit binary Up/down counter with control input M such that if M = 0 counter counts in down direction. Design the same using MUX controller method using D flip-flops.
(7 marks)
00
5.b.
Explain architecture of CPLD with the help of suitable diagram.
(6 marks)
00
OR
6.a.
Design Full adder using PLA.
(7 marks)
00
6.b.
Compare CPLD and FPGA.
(6 marks)
00
7.a.
Explain VHDL modeling styles with example.
(7 marks)
00
7.b.
Write VHDL programs for 3:8 decoder.
(6 marks)
00
OR
8.a.
What is VHDL ? Write features of VHDL. Explain the structure of VHDL module. Define entity and architecture for 2 input OR gate.
(7 marks)
00
8.b.
Explain the difference between concurrent and sequential statements with an example.
(6 marks)
00