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Computer Organization and Architecture Question Paper - Dec 18 - Information Technology (Semester 3) - Pune University (PU)
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Computer Organization and Architecture - Dec 18
Information Technology (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
1.a.
Multiply -7 and -3 using Booth’s algorithm.
(6 marks)
00
1.b.
Describe non-restoring division algorithm.
(6 marks)
00
Or
2.a.
What is an instruction cycle ? Explain with state diagram
(6 marks)
00
2.b.
Write a short note on register organization.
(6 marks)
00
3.a.
Draw and explain Hardwired Control Unit.
(6 marks)
00
3.b.
Write control sequence by execution of the instruction ADD $\left(\mathrm{R}_{1}\right), \mathrm{R}_{2}$ for single bus architecture.
(6 marks)
00
Or
4.a.
A direct mapped cache has the following parameters : Cache size = 1 K words, Block size = 128 words and main memory size = 64 K words. Specify the number of bits in TAG, BLOCK and WORDS in main memory address.
(6 marks)
00
4.b.
Explain K-way set associate mapping techniques with its merits and demerits.
(6 marks)
00
5.a.
Describe MIPS architecture with diagram.
(7 marks)
00
5.b.
Explain events of fetch cycle of MIPS pipeline.
(6 marks)
00
Or
6.a.
Explain types of hazards in pipeline architecture.
(6 marks)
00
6.b.
Explain the five stage pipelines with data paths and control path for MIPS architecture.
(7 marks)
00
7.a.
Explain closely coupled and loosely coupled microprocessor system.
(7 marks)
00
7.b.
Write a short note on Multi-core architecture.
(6 marks)
00
Or
8.a.
Write short notes on:
(i) NUMA
(ii) UMA
(iii) CC-NUMA
(6 marks)
00
8.b.
Explain Flynn's taxonomy for multiple processor organization.
(7 marks)
00
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