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Computer Organization Question Paper - Dec 18 - Computer Science (Semester 3) - Visveswaraya Technological University (VTU)
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Computer Organization - Dec 18
Computer Science (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Attempt any Five full questions , choosing ONE full question from each module.
(2) Draw neat diagrams wherever necessary.
Module-1
1.a.
Define the functions of following processor registers:
(4 marks)
00
i) MAR ii) MDR iii) IP iv) IR
1.b.
How to measure the performance of a computer? Explain.
(5 marks)
00
1.c.
Compute the content of 8 bit register namely R1 and R2 containing a value of $-17_{10}$ and $+98_{10}$ with inital carry bit as 1 after performing following shift or rotate operations 2 times.
(7 marks)
00
i) SHR R1 , 2 ii) SAR R1, 2p[Arithmetic shift]
iii) ROR R2, 2 iv) RCR R2, 2 [Rotate right with carry]
OR
2.a.
What is the need of processor stack? Explain a commonly used layout for information in a subroutine stack frame.
(6 marks)
00
2.b.
With relevant examples briefly explain about any 2 encoding types of machine instruction.
(5 marks)
00
3.c.
With a memory layout starting at address 'i' represent how "ABCD" is stored in big endian and little endian assignment scheme in a system of word length 16 bits.
(5 marks)
00
Module-2
3.a.
Explain how simultaneous interrupt requests from several I/O devices can be handles by processor through a single INTR line.
(6 marks)
00
3.b.
What is bus arbitration? With neat diagram explain about distributed arbitration process.
(6 marks)
00
3.c.
With a neat diagram, explain about data is read in asynchronous bus scheme.
(4 marks)
00
OR
4.a.
Explain with a neat block diagram , how hardware components needed for connecting a keyboard to a processor.
(8 marks)
00
4.b.
With a neat sequence diagram explain the process of , how output operation is carried between processor and output device connected to host through USB hub.
(8 marks)
00
Module-3
5.a.
With a neat diagram, explain the design of 2M x 32 memory module using 1M x 8 memory chips
(7 marks)
00
5.b.
Consider a cache consisting of 256 blocks of 16 words each, for a total of 4096 words and assume main memory is addressable by 16 bit address and it consists of 4K blocks. How many bits are there in each of Tag. block/ set and word fields for different mapping techniques?
(9 marks)
00
OR
6.a.
Explain the process of address translation with a neat diagram.
(6 marks)
00
6.b.
With a neat diagram discuss about organization of magnetic disk.
(6 marks)
00
6.c.
Calculate the average access time experienced by processor if miss penalty is 17 clock cycles and Miss rate is 10% and cache access time is 1 clock cycle.
(4 marks)
00
Module-4
7.a.
Design and explain the working of 16 bit carry look ahead adder built from 8 bit carry look ahead adder. Compare its performance with 16 bit ripple carry adder built from 8 bit ripple carry adder.
(10 marks)
00
7.b.
Calculate the product of $-2_{10}X + 14_{10}$ using bit pair recording multplier method. Why bit pair method is better than Booth algorithm?
(6 marks)
00
OR
8.a.
Perform the non-restoring division for the given binary numbers where dividend is $1011_{2}$ and divisor is $0101_{2}$ with all cycles.
(8 marks)
00
8.b.
Represent $0.625_{10}$ in double precision format and calculate the decimal value of A floating point number represented in single precision format as 4490000H.
(8 marks)
00
Module-5
9.a.
Write and discuss about micro-routine for complete execution of instruction Add (R1) , (R2) in single bus organization.
(8 marks)
00
9.b.
With a detailed block diagram explain about hardwired control unit
(8 marks)
00
OR
10.a.
With a block diagram explain briefly about an embedded processor.
(6 marks)
00
10.b.
Explain briefly about different ways of implementing multiprocessor system with supportive diagrams.
(6 marks)
00
10.c.
Write the control sequence for instruction Add R4, R5, R6 for 3 bus organization.
(4 marks)
00
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