1.a. List the steps needed to execute the machine instruction Add LOGA, RO in terms transfers between the processor and the memory along with some simple control commands. Assume that the instruction itself is stored in the memory at location INSTR and that this address is initially in register PC. The first two steps might be expressed as :

• Transfer the contents of Register PC to register MAR.
• Issue a Read command to the memory and then wait until it has transferred the requested word into a register MDR.

Remember to include the steps needed to update the contents of PC from INSTR to INSTR + 1 so that the next instruction can be fetched.

1.b. What is performance measurement? Explain the overall SPEC rating for the computer in a program suit.

2.a. With relevant figure define the little Endian and big Endian assignments.

2.b. Consider a computer that has a byte addressable memory organized in 32 bit words according to the big Endian scheme. A program reada ASCII characters entered at a keyboard and store them in successive byte location starting at location 1000. Show the contents of the two memory words at locations 1000 and 1004 after the name "Johnson" has been entered. (ASCII codes J=4AH, O = 6FH, n = 6EH, S = 73H)

2.c. Write about shift and rotate instruction with neat diagram and example of each.

3.a. With supporting diagram, explain the following with respect to interrupts:

i) Vectored interrupts

ii) Interrupt Nesting

iii) Simultaneous requests.

3.b. Three devices A, B, and C are connected to the bus of a computer. I/O transfers for all the devices use interrupt control. Interrupt nesting for devices A and B is not allowed, but interrupt requests from C may be accepted while either A or B is being services. Suggest different ways in which this can be accomplished in each of the following cases:

i) The computer has one interrupt request line.

ii) Two interrupt request line. INTR 1 and INTR2 ara available with INTR1 having higher priority. Specify when and how interrupts are enables and disable in each case.

3.c. Illustrate the tree structure of USB with diagram.

4.a. With a neat diagram, explain the centalized arbitation and distributed bus arbitation scheme.

4.b. With neat timing diagram illustrate the asynchronous bus data transfer during an input operation. Use handshake scheme.

5.a. Draw a diagram and explain the working of 16 megabits DRAM chip configured as 2M x 8.

5.b. Describe organization of an 2M x 32 memory using 512k x 8 memory chips.

6.a. Discuss in detail the working of set associative mapped cache with two blocks per set with relevant data.

6.b. Define the following with respect to cache memory :

i) valid bit ii) Dirty data

iii) Stale data iv) Flush the cache

6.c. A block-set associative cache consists of a total of 64 blocks divided into 4 blcks sets. The main memory contains 4096 bocks, each consisting of 128 words.

i) How many bits are there in the main memory address?

ii) How many bits are there in each of the TAG, SET ans WORD fields?

7.a. Convert the following pairs of decimal numbers to 5 bit signed 2's complement numbers and add them. State whether or not overflow occurs in each case.

i) 5 and 10 ii)-14 and 11

iii) -5 and 7 iv) -10 and -13

7.b. Design the 16 bit carry look ahead using 4-bit adder. Also unite the expression for $C_{i+1}$

7.c. Draw the two n-bit number x and y to perform addition/subtraction.

8.a. WIth an example explain the Booths algorithm to multiply two signed operands.

8.b. Multiply each of the following pairs of signed 2's complement number using the Booths algorithm.(A = multiplicated and B= multipler)

i) A = 010111 and B = 110110

ii) A = 110011 and B = 101100

iii) A = 110101 and B = 011011

iv) A = 001111 and B = 001111

9.a. Discuss with neat diagram, the single bus organization of the data path inside a processor.

9.b. Write the sequence of control steps required for single bus structure for each if the following instructions.

i) Add the contents of memory location NUM to register RI.

ii) Add the contents of memory location whose address is at memory location NUM to register RI.

10.a. Discuss the microwave oven with neat block diagram.

10.b. Discuss the digital camera with neat diagram.