1.a. Explain top-down design methodology with an example.

1.b. Explain the typical design flow for designing VLSI IC circuits, with a neat flow chart.

2.a. Explain Bottom -up design methodology with an example.

2.b. Explain the different levels of abstraction used for programming in verilog.

3.a. Explain system tasks and compiler directives in verilog.

3.b. What are the basic components of a module? Explain all the components of a verilog module with a neat block diagram.

3.c. Write verilog description of SR Latch. Also write simulus code.

4.a. Write a note on: i) Registers ii) Nets iii) Arrays iv) Parameters (vi) memories.

4.b. Declare a top -level module “Stimulus” . Define Reg_in (4 bit) and Clk (1 bit) as register variables and Reg_out (4 bits) as wire. Instantiate the module “shift -reg” in “stimulus” block and connect the ports by ordered list. Declare A (4 bit) and clock (1 bit) as inputs and B (4 bit) as output in “shift -reg” module. (No need to show internals ). Write a verilog code for the above.

5.a. Write the verilog description of 4 bit ripple carry adder at gate level abstraction, with a neatblock diagram. Also, write stimulus block.

5.b. What would be the output of the following: a = 4'b1010, b = 4'b1111 i) a & b ii) a && b iii) & a iv) a >> 1 v) a >>> 1 vi) y = {2{a}} vii)a ^ b viii) z = {a, b}.

6.a.A full subtractor has three 1 -bit inputs x, y and z (previous borrow) and two 1 -bit outputs D(Difference) and B(Borrow). The logic equations are Write verilog description using dataflow modeling. Instantiate the subtractor module inside a stimulus block and test all possible combinations of inputs x, y and z.

6.b. Design 4:1 multiplexer using gate level modeling or structural description. Write stimulus block.

7.a. Explain structured procedure statements in verilog.

7.b. Write a verilog behavioral 8:1 multiplexer program using case statement.

7.c. Explain casex and casez statements in verilog.

8.a. Explain procedural assignment statements in verilog.

8.b. Explain sequential and parallel blocks with examples.

8.c. Write a verilog code to find the first bit with a value 1 in Flag = 16'b 0010_0000_0000_0000.

9.a. Explain the design tool flow followed in VLSI design with a neat flow diagram.

9.b. Write VHDL Data flow description of 1 Bit full Adder.

10.a.Explain the relationship between a design entity and its entity declaration and architecture body in VHDL.

10.b. Write VHDL structural description of 1 Bit Full Adder.