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Digital System Design Question Paper - Dec 18 - Electrical And Electronics (Semester 3) - Visveswaraya Technological University (VTU)
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Digital System Design - Dec 18
Electrical And Electronics (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Module-1
(6 marks)
00
1.a. Define a combinational circuit. With block diagram, explain the steps involved in designing the combinational circuit.
1.b.
Simplify the Boolean function using K-map F(A, B, C, D) = $\Sigma m(0,4,5,8,12,13,16,20,21,24,28,29)$
(6 marks)
00
1.c.
Define the following terms:
i) Maxterm
ii) Minterm
iii) Canonical SOP
iv) Canonical POS
(4 marks)
00
Or
2.a.
Simplify the following function using 3 -variable MEV K-map. f(A, B, C, D) = $\Sigma m(0,1,3,5,6,11,13)+d(4,7)$
(6 marks)
00
2.b.
Simplify the given Boolean function using Quine-McCluskey method.
f(A, B, C, D) $=\sum m(7,9,12,13,14,15)+d(4,11)$
(5 marks)
00
Module-2
(6 marks)
00
3.a. Design a combinational circuit to convert BCD to Excess-3.
3.b.
Implement the multiple functions $f_{1}(a, b, c, d)=\sum m(1,4,8,13)$
$f_{2}(a, b, c, d)=\sum m(2,7,13,14)$ using two 74138 (3 to 8) decoders.
(6 marks)
00
3.c.
Implement a full adder using 4:1 multiplexed.
(4 marks)
00
Or
4.a.
Define magnitude comparator. Design a 4-bit binary comparator and implement with
suitable logic gates
(10 marks)
00
4.b.
Implement the following function $f(a, b, c, d)=\sum m(0,2,6,10,11,12,13)+d(3,8,14)$ using 8:1 multiplexer.
(6 marks)
00
Module-3
(6 marks)
00
5.a. Explain with waveforms a switch de-bouncer using SR latch
5.b.
Explain the working of Master-Slave S-K flip-flop with the help of logic diagram, functional table, logic symbol.
(6 marks)
00
5.c.
Obtain the characteristic equation for J-K and S-R flip-flops.
(4 marks)
00
Or
6.a.
With a neat logic diagram, explain the working of positive edge triggered D-flip-flop.
(6 marks)
00
6.b.
Design a synchronous counter to give a counting sequence 0, 2, 3, 6, 5, 1, 0… using J-K F/F.
(6 marks)
00
6.c.
With the help of a schematic diagram, explain a serial shift register can be transformed into a
(i) ring counter (ii) Johnson counter.
(4 marks)
00
Module-4
(6 marks)
00
7.a. Explain Mealy and Moore models of a clocked synchronous sequential circuits.
7.b.
A sequential circuit has one input and one output state diagram is as shown in Fig.Q7(b). Design the sequential circuit with J-K F/F.
(10 marks)
00
Or
8.a.
Analyze the sequential circuit shown in Fig.Q8(a). Construct the excitation table, transition
table, state table and state diagram for sequential circuit shown in Fig.Q8(a).
(10 marks)
00
8.b.
Write the differences between combinational and sequential circuits.
(6 marks)
00
Module-5
(6 marks)
00
9.a. With general syntax and suitable example, explain the logical and relational operators in VHDL.
9.b.
Explain the various data types available in VHDL
(10 marks)
00
Or
10.a.
What are the different steps used for simulation and synthesis?
(8 marks)
00
10.b.
Mention different styles of descriptions in HDL. Write a short note on behavioral description
and also HDL code for half adder using behavioral description.
(8 marks)
00
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