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Verilog HDL Question Paper - Dec 17 - Electronics And Communication Engineering (Semester 5) - Visveswaraya Technological University (VTU)
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Verilog HDL - Dec 17
Electronics And Communication Engineering (Semester 5)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Module-1
1.a. Explain a¹ typical design flow for designing VLSI IC circuit using block diagram.
(6 marks)
00
1.b. Explain top down design methodology and button up design methodology.
(10 marks)
00
2.a. With a block diagram diagram of 4 bit Ripple carry counter,explain the design hierarchy.
(10 marks)
00
2.b. Explain the trend in Hardware Description Languages (HDLs).
(6 marks)
00
Module-2
3.a. With a neat block diagram, explain the components of verilog module.
(6 marks)
00
3.b. Explain the following data type with an example in verilog:
(i) Nets (ii) Register (iii) Integers (iv) Real (v) Time Register.
(10 marks)
00
OR
4.a. Explain the port connection rules.
(6 marks)
00
4.b. Explain the two methods of connecting ports to external signal with example.
(10 marks)
00
Module-3
5.a. What is rise, fall and Turn-off delays? How they are specified in verilog?
(6 marks)
00
5.b. Design a 2-to-1 multiplexer using bufifl gates. The delay specification for these gates are as follows:
![enter image description here][1]
Write gate level description and stimulus in verilog.
(6 marks)
00
OR
6.a. Write a verilog dataflow level of abstraction for 4-to-1 multiplexer using conditional operator.
(6 marks)
00
6.b. Write a verilog data flow description for 4-bit Full adder with carry lookahead.
(10 marks)
00
Module-4
7.a. Explain the blocking assignment statements and non-blocking assignment statements with relevant examples.
(8 marks)
00
7.b. Write a note on the following loop statement:
(i) While Loop (ii) Forever Loop.
(8 marks)
00
OR
8.a. Explain sequential and parallel blocks with examples.
(8 marks)
00
8.b. Write a verilog program for 8-to-1 multiplexer using case statement.
(8 marks)
00
Module-5
9.a. Explain the Synthesis process with a block diagram.
(8 marks)
00
9.b. Write a VHDL program for two 4-bit comparator using data flow description.
(8 marks)
00
OR
10.a. Explain the declaration of constant, variable and signal in VHDL with example.
(8 marks)
00
10.b. Write a VHDL program for half adder in behavioral description.
(8 marks)
00
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