1.a. Write the truth table of the logic circuit having 3 inputs: A, $B$ and $C$ and an output $Y=A B \overline{C}+\overline{A B C}+A B C$ . Also simplify the Boolean expression and implement the logic circuit using NAND gates only. \lt/div\gt \ltspan class='paper-ques-marks'\gt(6 marks)\lt/span\gt \ltspan class='paper-page-id'\gt00\lt/span\gt \lt/div\gt \ltDIV class='paper-question'\gt \ltDIV class='paper-ques-desc'\gt \ltb\gt1.b. \lt/b\gt Using Quine - McCluskey method, simplify: $\mathrm{f}(\mathrm{a}, \mathrm{b}, \mathrm{c}, \mathrm{d})=\sum \mathrm{m}(2,3,4,5,13,15)+\mathrm{dc}$ $(8,9,10,11) .$

2.a. Define Canonical Minterm formula and Canonical maxterm formula with an example for each.

2.b. Simplify the Boolean expression using 'd' as MEV for $\mathrm{f}(\mathrm{a}, \mathrm{b}, \mathrm{c}, \mathrm{d})=\sum \mathrm{m}(2,3,4,5,8,9,10,11,13,15)$

2.c. Design a three input, A B and C and output ; 'Y' ; minimal two level gate combinational circuit which has an output equal to 'zero' when majority of its inputs are at logic 'I'.

3.a. Design a comparator to check if two N-bit numbers are equal. Configure this using cascaded stages of $1-$ bit comparator.

3.b. Write the compressed truth table for a 4 to 2 line priority encoder with a valid output and simplify the same using $\mathrm{K}$ -Map. Design the logic circuit as well.

3.c. Implement the following Boolean function using a $4 : 1 \mathrm{MUX}$ with $\mathrm{A}$ and $\mathrm{B}$ as select lines $\mathrm{Y}=\mathrm{f}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\sum m(0,1,2,4,6,9,12,14) .$

4.a. Write a short note on 4 -bit parallel Adder.

4.b. Using active high output $3 : 8$ line decoder, implement the following functions

$f_{1}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\sum m(0,1,2,5,7,11,15)$

$\mathrm{f}_{2}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\sum \mathrm{m}(1,3,4,11,13,14)$

4.c. Design an $8 : 1$ MUX Tree using only $2 : 1$ multiplexers.

5.a. With a neat logic diagram, explain working of a Master slave $J \mathrm{K}$ Flip-Flop along with waveforms. Also brief about Race-around condition.

5.b. Convert a $T-$ Flip-Flop to a $D-$ Flip-Flop.

5.c. Write a short note on shift Registers.

6.a. Design Synchronous Mod - 6 counter using SR Flip-Flops.

6.b. Compare Asynchronous and Synchronous counters.

6.c. Explain working of a 4 -bit binary ripple down counter configured using negative edge triggered JK Flip-Flop with timing diagram.

7.a. Explain Melay and Moore models with neat block diagrams.

7.b. Analyse the synchrononous circuit of the Fig $\mathrm{Q} 7(\mathrm{b})$ shown below,

i) Write down excitation and output functions.

ii) Form the excitation and state tables

iii) Give description of the circuit operation.

8.a. Define state, present state, state diagram and state table.

8.b. Construct Moore and Melay model state diagrams to detect input sequence 10110 . When the input pattern is detected, output $^{*} Z^{\prime}$ is asserted HIGH.

8.c. Construct a state diagram for synchronous decade UP/DOWN counter. The mode control; 'M' decides the pattern of counting operation. When $M=0$ 'Counter counts UP and when $M=1 ;$ the counter counts DOWN. When the counter reaches terminal count $Y=1$ (for UP count) and $Z=1$ (for DOWN count). Label the state diagram in M/YZ mode.

9.a. Mention styles/lypes of HDL description. Explain behavioral type with half adder example in both VHDL and verilog.

9.b. Compare VHDL and verilog.

9.c. Explain verilog data types.

10.a. Tabulate Rotate operators used in HDL with example operand $\mathrm{A}=1110 .$

10.b. Draw the block diagram of 3 -bit carry look ahead adder. Write verilog code for the same.