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Analog Electronic Circuits Question Paper - Jun 17 - Electrical And Electronics (Semester 3) - Visveswaraya Technological University (VTU)
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Analog Electronic Circuits - Jun 17

Electrical And Electronics (Semester 3)

Total marks: 80
Total time: 3 Hours

Note: Answer any FIVE full questions, choosing ONE full question from each module.

Module-1

1.a. Explain DC analysis of collector to base bias circuit.
(5 marks) 00

1.b. For the biasing circuit as shown in Fig.Q1(b), calculate $\mathrm{I}_{\mathrm{E}}$, $\mathrm{I}_{\mathrm{C}}$, $\mathrm{V}_{\mathrm{C}}$ and $\mathrm{V}_{\mathrm{CE}}$. Given that $V_{E E}=-8 V, R_{E}=2.2 k \Omega, R_{B}=1.8 k \Omega, \beta=100$

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(5 marks) 00

1.c. For emitter stabilized bias circuit $\mathrm{V}_{\mathrm{CC}}$ = 10V, $\mathrm{R}_{\mathrm{C}}$ = 1K$\Omega$, $\mathrm{R}_{\mathrm{E}}$ = 500$\Omega$, $\beta$ = 100. Calculate $\mathrm{I}_{\mathrm{B}}, \mathrm{I}_{\mathrm{C}}, \mathrm{V}_{\mathrm{CE}}, \mathrm{V}_{\mathrm{E}}$ and $\mathrm{V}_{\mathrm{C}}$. Draw the circuit diagram
(6 marks) 00

OR

2.a. For the fixed bias circuit, derive expressions for $\mathrm{S}_{\mathrm{ICO}}, \mathrm{S}_{\beta}$ and $\mathrm{S}_{\mathrm{VBE}}$
(6 marks) 00

2.b. For a voltage divider bias circuit $R_{C}=1 k \Omega, R_{E}=470 \Omega$, $\mathrm{R}_{1}=10 \mathrm{k} \Omega, \mathrm{R}_{2}=5 \mathrm{k} \Omega,, \beta=100$. Determine the stability factor $\mathrm{S}_{\mathrm{ICO}}$ Draw the circuit diagram
(5 marks) 00

2.c. For the circuit shown in Fig.Q2(c), calculate the value of $R_{E}$ that just saturates the transistor when $V_{i}$= + 5V. Given that $\mathrm{R}_{\mathrm{C}}=1 \mathrm{k} \Omega, \mathrm{\beta}=100$ $\mathrm{V}_{\mathrm{CC}}=5 \mathrm{V}, \mathrm{V}_{\mathrm{CEsat}}$ $=0.2 \mathrm{V}$

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(6 marks) 00

Module-2

3.a. Explain hybrid equivalent model for a transistor. Develop h-paramcter model for a transistor in CE, CB and CC modes.
(8 marks) 00

3.b. For the common base circuit shown in Fig.Q3(b), $\mathrm{R}_{\mathrm{C}}=10 \mathrm{k} \Omega, \mathrm{R}_{\mathrm{E}}=5 \mathrm{k} \Omega, \mathrm{R}_{\mathrm{S}}=1 \mathrm{k} \Omega$, $\mathrm{R}_{\mathrm{L}}=12 \mathrm{k} \Omega, \mathrm{h}_{\mathrm{ib}}=22 \Omega$ $hob =0.49 \mu \mathrm{A} / \mathrm{V}, \quad \mathrm{h}_{\mathrm{rb}}=2.9 \times 10^{-4}$ $h_{f b}=-0.98$, Use extract h-parameter model. Calculate $\mathrm{A}_{\mathrm{l}}, \mathrm{Z}_{\mathrm{l}}, \mathrm{A}_{\mathrm{V}}$ and $\mathrm{A}_{\mathrm{VS}}$

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(8 marks) 00

OR

4.a. Explain the low frequency response by considering input RC network, output RC network.
(8 marks) 00

4.b. Calculate the high frequency response of amplif‌ier circuit. Assume $\mathrm{R}_{\mathrm{C}}=2.2 \mathrm{k} \Omega, \mathrm{R}_{\mathrm{E}}=1 \mathrm{k} \Omega$, $\mathrm{R}_{1}=68 \mathrm{k} \Omega,, \mathrm{R}_{2}=22 \mathrm{k} \Omega, \mathrm{Rs}=680 \Omega, \beta=100$, $\mathrm{C}_{\mathrm{W}_{\mathrm{i}}}=6 \mathrm{pF}, \mathrm{C}_{\mathrm{Wo}}=8 \mathrm{pF}, \mathrm{C}_{\mathrm{cc}}=1 \mathrm{pF}, \mathrm{C}_{\mathrm{bc}}=20 \mathrm{pF}$, $\mathrm{C}_{\mathrm{bc}}=4 \mathrm{pF}, \mathrm{h}_{\mathrm{ie}}=1.1 \mathrm{k} \Omega, \mathrm{V}_{\mathrm{CC}}=10 \mathrm{V}$. Draw the circuit diagram. $\mathrm{R}_{\mathrm{L}}=10 \mathrm{k} \Omega$
(8 marks) 00

Module-3

5.a. For the 3-stage amplif‌ier circuit as shown in Fig.Q5(a), $\mathrm{R}_{\mathrm{S}}=1 \mathrm{k} \Omega, \mathrm{R}_{\mathrm{C} 1}=3.3 \mathrm{k} \Omega, \mathrm{R}_{\mathrm{E} 2}=4.7$ $\mathrm{k} \Omega, \mathrm{h}_{\mathrm{ie}}=2 \mathrm{k} \Omega, \mathrm{h}_{\mathrm{fe}}=50, \mathrm{h}_{\mathrm{re}}=0, \mathrm{h}_{\mathrm{oc}}=0$, calculate the overall voltage gain $A_{V}$ and overall $Z_{0}$

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(8 marks) 00

5.b. For Darlington emitter follower circuit, obtain an expression for overall current gain $A_{I}$.
(8 marks) 00

OR

6.a. For voltage series feedback topology obtain expressions for $A_{V}$ and $R_{if}$.
(8 marks) 00

6.b. For the current series feedback as shown in Fig.6(b), $\mathrm{R}_{\mathrm{L}}=2.2 \mathrm{k} \Omega, \mathrm{R}_{\mathrm{E}}=1.2 \mathrm{k} \Omega,, \mathrm{R}_{\mathrm{B}}=1 \mathrm{k} \Omega$, $\mathrm{h}_{\mathrm{ie}}=1.1 \mathrm{k} \Omega, \mathrm{h}_{\mathrm{fe}}=50,$ calculate $\mathrm{G}_{\mathrm{M}}, \beta, \mathrm{D}, \mathrm{G}_{\mathrm{MF}}$

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(8 marks) 00

Module-4

7.a. For transformer coupled class A power amplifier, obtain DC and AC Operation and expression for maximum eff‌iciency.
(8 marks) 00

7.b. A class B push pull amplif‌ier drives a load of $16\Omega, V_{CC} = 25V$, number of turns in primary = 200 and that in secondary is 90. Calculate maximum power output, eff‌iciency and maximum power dissipation per transistor.
(8 marks) 00

OR

8.a. State and explain Barkhausen criterion for sustained oscillations.
(5 marks) 00

8.b. Derive an expression for frequency of ocillations in Wien bridge oscillator.
(8 marks) 00

8.c. Calculate the frequency of oscillations of colpitts oscillator if $\mathrm{C}_{1}=150 \mathrm{pF}, \mathrm{C}_{2}=1.5 \mathrm{nF}$ and $\alpha=50 \mu H$
(3 marks) 00

Module-5

9.a. What are the advantages and drawback of FET vs BJT?
(5 marks) 00

9.b. For the circuit shown in Fig.Q9(b), calculate $\mathrm{V}_{\mathrm{GSQ}}, \mathrm{I}_{\mathrm{DQ}}\mathrm{V}_{\mathrm{DSQ}},$ and $\mathrm{V}_{\mathrm{D}}$ given $\mathrm{I}_{\mathrm{DSS}}=10 \mathrm{mA}$ and $V_{p} = -4V$.

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(5 marks) 00

9.c. For JFET, obtain the condition for zero current drift.
(6 marks) 00

OR

10.a. Explain construction, working and characteristics of n-channel depletion type MOSFET.
(8 marks) 00

10.b. For the circuit shown in Fig.Q10(b), calculate $\mathrm{V}_{\mathrm{GS}}, \mathrm{I}_{\mathrm{D}}$ and $\mathrm{V}_{\mathrm{DS} .}$ Given, $\mathrm{I}_{\mathrm{D}}$ ON $=6 \mathrm{mA}$

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(8 marks) 00

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