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Digital System Design Question Paper - Dec 17 - Electrical And Electronics (Semester 3) - Visveswaraya Technological University (VTU)
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Digital System Design - Dec 17
Electrical And Electronics (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Module-1
(4 marks)
00
1.a. With basic block diagram, explain the combinational logic circuit
1.b.
Reduce the following function using K-map technique and implement using basic gates
i) f(P, Q, R, S) = $\sum m(0,1,4,8,9,10)+d(2,11)$
ii) f(A, B, C, D)= $\pi M(0,2,4,10,11,14,15)$
(12 marks)
00
Or
2.a.
Simplify using the Quine-Mcclusky minimization technique.
Y = f(a, b, c, d) = $\sum m(0,2,8,10)$.
(8 marks)
00
2.b.
Simplify the given function using MEV technique.
f(a, b, c, d) = $\Sigma(2,3,4,5,13,15)+\Sigma d(8,9,18,11)$.
(8 marks)
00
Module-2
(5 marks)
00
3.a. With the aid of general structure, clearly distinguish between a decoder and encoder.
3.b.
Implement following multiple output function using one 74LS138 and external gates.
$\mathrm{F}_{1}(\mathrm{A}, \mathrm{B}, \mathrm{C})=\sum \mathrm{m}(1,4,5,7)$
$\mathrm{F}_{2}(\mathrm{A}, \mathrm{B}, \mathrm{C})=\pi \mathrm{M}(2,3,6,7)$
(6 marks)
00
3.c.
Draw the interfacing diagram of ten keypad interface to a digital system using decimal to BCD encoder (IC 74LS147: Decimal to BCD priority encoder)
(5 marks)
00
Or
4.a.
Design a full adapter by constructing the truth table and simplify the output equations.
(6 marks)
00
4.b.
Write a truth table for two-bit magnitude compartor. Write the Karnaugh map for each output of two bit magnitude comparator and the resulting equation.
(10 marks)
00
Module-3
(8 marks)
00
5.a. What is the difference between a flip-flop and a latch? With logic diagram and truth table explain the operation of gated SR latch.
5.b.
Explain the operation of Master slave JK Flip-Flop along with its circuit diagram.
(8 marks)
00
Or
6.a.
Explain the working principle of four bit binary ripple counter, with the help of a logic diagram, timing diagram and counting sequence.
(10 marks)
00
6.b.
With logic diagram and counting sequence explain Mod - 4 ring counters.
(6 marks)
00
Module-4
(8 marks)
00
7.a. Distinguish between Moore and Melay model with necessary block diagram.
7.b.
Give output function transition table and state diagram by analyzing the sequential circuit shown in Fig. Q7(b).
(5 marks)
00
Or
8.a.
Write the basic recommended steps for the design of a clocked synchronous sequential circuit.
(6 marks)
00
8.b.
Design a synchronous counter using J-K flip flops to count the sequence 0, 1, 2, 4, 5, 6, 0, 1, 2. Use state diagram and state table.
(10 marks)
00
Module-5
(6 marks)
00
9.a. Explain brief history of HDL and structure of HDL module.
9.b.
List the classification of VHDL data types. Compare the VHDL data types and Verilog data types.
(10 marks)
00
Or
10.a.
Explain signal declaration and signal assignment statements with relevant example.
(6 marks)
00
10.b.
Write a data flow description VHDL for a system that has three 1-bit inputs a (1), a(2) and a(3) one 1-bit output b. The least significant bit is a(1) ; and b is 1, only when (a(1) a(2) a(3)) = 1, 3 ,6 or 7 (all in decimal) otherwise b is 0. Derive a minimized Boolean function of the system and write the data flow description.
(10 marks)
00
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