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Digital System Design Question Paper - Jun 17 - Electrical And Electronics (Semester 3) - Visveswaraya Technological University (VTU)
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Digital System Design - Jun 17
Electrical And Electronics (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
1.a.
Module-1
(6 marks)
00
Define combination logic, canonical logic, canonical SOP, canonical POS, with examples.
1.b.
Place the following equations into proper canonical form:
(4 marks)
00
1.c.
Solve the following Boolean equation using four variable Karnaugh map and implement the simplified equation using minimum number of logic gates.
$f(a, b, c, d)=\Sigma(0,5,7,8,10,13)+d(2,4,14,15)$
.
(6 marks)
00
Or
2.a.
Solve four variable expression using Quine McClusky minimization technique. $K=f(a, b, c, d)=\pi M(0,3,4,7,8,10,12,14)+d(2,6)$
(8 marks)
00
2.b.
Simplify the Boolean expression using a 3-variable VEM, with 'Z' as MEV
$f(w, x, y, z)=\Sigma m(3,4,5,7,8,11,12,13,15)$.
(8 marks)
00
Module-2
(6 marks)
00
3.a. Implement 3-bit binary to gray code conversion circuit using IC 74139. Draw neat diagram truth table with switching equations in SOP form.
3.b.
Implement the following multiple output functions for active low outputs using IC74138.
(4 marks)
00
3.c.
What are multiplexers? Implement the function using 8:1 MUX.
(6 marks)
00
Or
4.a.
Implement 4-bit parallel adder/subtractor using 4-full adder blocks. If $C_{i n}=0$ the circuit should act as adder and if $C_{i n}=0$ = 1 the circuit should act as substractor. Explain its operation by considering examples.
(6 marks)
00
4.b.
What is the problem associated with the parallel adder? Explain the method of correction it, with suitable circuit and equations.
(6 marks)
00
Module-3
(8 marks)
00
5.a. Explain the operation of Master-Slave JK flip-flop with logic diagram, truth table symbol and timing diagram.
5.b.
Distinguish between sequential circuits and combinational circuits.
(4 marks)
00
5.c.
Explain the operation of basic bistable element, using two-inverter configuration.
(5 marks)
00
Or
6.a.
Derive characteristics equations for SR flip-flop and JK flip-flop, represent truth table and K-maps.
(4 marks)
00
6.b.
Explain the operation of 4-bit ring counter and twisted ring counter.
(6 marks)
00
6.c.
Design synchronous MOD6 counter using clocked 'D' flip flops for the sequence 0$\rightarrow 2 \rightarrow 3 \rightarrow 6 \rightarrow 5 \rightarrow 1$, again, 0... represent application table, excitation table and logic diagram.
(6 marks)
00
Module-4
(8 marks)
00
7.a. Define state variables and excitation variables and write a note on Moore and Mealy sequential models.
7.b.
For the logical diagram shown in Fig.Q.7(b), find excitation table, state table and state diagram.
(8 marks)
00
Or
8.a.
Analyze the circuit shown in FigQ.8(a), obtain excitation table, state table and state diagram.
(5 marks)
00
8.b.
Design the sequential logic circuit for single input single output system shown in Fig.Q.8(b) state diagram using clocked 'D' flip-flop
(6 marks)
00
Module-5
(8 marks)
00
9.a. Explain the structure of VHDL and verilog module with example code for each and compare them.
9.b.
List the various styles/types of description in VHDL and verilog. Explain VHDL structural description with example code.
(8 marks)
00
Or
10.a.
Explain the structure of data flow description in VHDL and verilog, using suitable example code.
(8 marks)
00
10.b.
Write VHDL and verilog code for 2 x 2 magnitude comparator for all input combinations.
(8 marks)
00
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