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Explain VHDL format in detail.
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A VHDL design begins with an ENTITY block that describes the interface for the design. The interface defines the i/p and o/p logic signals of the ckt to be designed.

The ARCHITECTURE Block describes the internal operation of the design.

Fig below shows the VHDL program structure.

enter image description here

Entity entity-name is

[port (interface-signal-declaration;]

End [entity] [entity – name] ;

Architecture architecture-name of entity – name is

[declarations]

Begin

Architecture Body

End[architecture] [architecture name];

e.g. VHDL (format) example for NOR latch

enter image description here

Library ieee;

Use ieee_std_logic_1164.all;

Entity latch is

Port (s,r : m std_logic;

Q,rq:out std_logic);

End later;

Architecture flip flop of latch is

Begin

Q < = n more nq;

Nq < = s nor q;

End flip flop;

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