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Write VHDL program for Ex-NOR gate?
written 5.8 years ago by
teamques10
★ 69k
|
modified 3.2 years ago
by
sagarkolekar
★ 11k
|
Ex-NOR gate
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Program:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gate IS
PORT (A, B : IN STD_ WORK;
Y : OUT STD_WORK);
END gate;
Architectural behavioral of gate is
Begin
Process (A, B)
Begin
If A = 0 and B = 0 then Y $\leftarrow$ ‘1’
Else if A = 0 AND B = 0 then Y $\leftarrow$ ‘0’
Else if A = 1 and B = 0 then Y $\leftarrow$ ‘0’
Else if A = 1 and B = 1 then Y $\leftarrow$ ‘1’
End if
End process
End behavioral;
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