VHDL program for half subtractor.

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written 6.5 years ago by

teamques10 ★ 70k

modified 3.7 years ago by

sagarkolekar ★ 11k

vlsi design

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written 3.7 years ago by

sagarkolekar ★ 11k

VHDL program for half subtractor:

Continued: LIBRARY ieee;

USE ieee.std_logic_1164_all;

Entity HS IS

PORT (A, B : IN STD_LOGIC;

Diff,Borrow: OUT STD_Logic);

END HS;

ARCHITECTURE BEHAVIOUR OF HS IS

BEGIN DIFF < = A XOR B;

BORROW < = (NOT A) AND B;

END BEHAVIOUR;

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