**1 Answer**

written 2.4 years ago by |

**VHDL program for half subtractor:**

Continued: LIBRARY ieee;

USE ieee.std_logic_1164_all;

Entity HS IS

PORT (A, B : IN STD_LOGIC;

Diff,Borrow: OUT STD_Logic);

END HS;

ARCHITECTURE BEHAVIOUR OF HS IS

BEGIN DIFF < = A XOR B;

BORROW < = (NOT A) AND B;

END BEHAVIOUR;

A shift register which can shift the data in only one direction called as unidirectional shift register.

A shift reg. which can shift data in both the directions is called as Bi-directional shift register.

Applying the same logic a shift register which can shift the data in both directions as well as load it parallel, then it is called as universal shift register.

It is capable of performing following operations:

1] Parallel loading (PIPO).

2] Left shift.

3] Right shift.

- For serial left operation the i/p is applied to serial i/p which goes to AND gate in figure. Whereas for shift right operation, the serial i/p is applied to D i/p (of AND – 8)

**Operation.**

**1] With M = 0 shift right operation:**

If M = 0 then AND gate 1,3,5,7 and 9 are enabled whereas remaining 2,4,6,8 and 10 are disabled. Clock 1 is s/g provided as for all ff for right suit operation. Serial i/p is provided through AND gates and data will shift from A ff to D ff bit by bit.

**2] With M = 1 shift left operation:**

If M = 1 then the AND gates 2,4,6,8 and 10 are enabled whereas the remaining gates 1,3,5,7 and 9 are disabled. Clock s/g is provided through AND gate 10 to all flip flops.