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Define the following. (i) Slew rate (ii) CMRR (iii) Input offset voltage (iv) Output offset voltage (v) PSRR
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(i) Slew Rate :

One of the important frequency related parameter of an op-amp is the slew rate. The slew rate is the maximum rate of change of output voltage caused by a step input voltage and is usually specified in V/µS. For example 1V/µS slew rate means that the output rises or falls by 1V in one microseconds. Ideally slew rate is infinite which means that op-amp’s output should be changed instantaneously in response to input step voltage. Practical op-amp are available with slew rates from 0.1V/µS to well above 1000V/µS.

(ii) CMRR :

Common Mode Rejection Ratio is defined in several essentially equivalent ways by the various manufacturers. Generally, it can be defined as the ratio of the differential gain AD to the common mode gain $A_{CM}$ that is,

$$CMRR = \frac{A_D}{A_{CM}}$$

For 741C, CMRR is typically 90dB. CMRR is usually expressed under the test condition that the input source resistance $R_S$ ≤ 10kΩ. Higher the value of CMRR, better is the matching between two input terminals and smaller the output common-mode voltage.

(iii) Input offset voltage :

Input offset voltage $V_io$ is the differential input voltage that exists between two input terminals of an op-amp without any external inputs applied. In other words, it is the amount of the input voltage that should be applied between two input terminals in order to force the output voltage to zero. Since this voltage could be positive or negative its absolute value is listed on the data sheet. For 741C, the maximum value is 6mV.

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(iv) Output offset voltage :

  • The output offset voltage VOO is caused by mismatching between two input terminals. Even though all the components are integrated on the same chip, it is not possible to have two transistors in the input differential amplifier stage with exactly the same characteristics.

  • This means that the collector currents in these two transistors are not equal, which causes a differential output voltage from the first stage.

  • The output of first stage is amplified by following stages and possibly aggravated by more mismatching in them. Thus output voltage caused by mismatching between two input terminals is the output offset $V_{OO}$.

  • The output offset voltage is a dc voltage; it may be positive or negative in polarity depending on whether the potential difference between two input terminals is positive or negative.

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(v) PSRR :

The change in an op-amp’s input offset voltage due to variations in supply voltage is called as power supply rejection ratio (PSRR) or called as supply voltage rejection ratio (SVRR). This term is expressed in microvolts per volt or decibels. For 741C, PSRR=150µV/V, lower the value of PSRR, better the op-amps.

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