We have seen that verification is a set of activities that ensures correct implementation of specific functions in a software. What is the need of verification? Can't we test the software in the final phase of SDLC? Under the V&V process, it is mandatory that verification is performed at every step of SDLC. Verification is needed for the following:
- If verification is not performed at early stages, there is always a chance of mismatch between the required product and the delivered product. Suppose, if requirements are not verified, then it may lead to situations where requirements and commitments are not clear. These things become important in case of non-functional requirements and they increase the probability of bugs.
- Verification exposes more errors.
- Early verification decreases the cost of fixing bugs,
- Early verification enhances the quality of software.
Everything Must be Verified
In principle, all the SDLC phases and all the products of these processes must be verified.
Results of Verification May Not be Binary
Verification may not just be the acceptance or rejection of a product. There are many verification activities whose results cannot be reduced to a binary answer. Often, one has to accept approximations. For example, sometimes correctness of a requirement cannot be rejected or accepted outright, but can be accepted with a degree of satisfaction or rejected with a certain degree of modification.
Even Implicit Qualities Must be Veritied
The qualities desired in the software are explicitly stated in the SRS. However, those requirements which are implicit and not mentioned anywhere must also be verified.
Checklist and Verification Activities
Checklists are used for the verification of various phases of SDLC. A checklist is an effective quality tool to check and assess the completion of all the activities in an SDLC phase. The checklist can be considered same as a do-list as we prepare in our daily life for checking the completion of our tasks.
Since all the verification activities are performed in connection with the different phases of SDLC, the following verification activities have been identified:
- Verification of requirements and objectives
- Verification of high level design
- Verification of low level design
- Verification of coding (unit verification)