The drain charecteristics of FET consist of three regions:

1. Linear or ohmic region where voltage VDS is small and ID is neary proportional to VDS
2. The saturation region (or the active region) where ID is fairly constant and independent of VDS.
3. Break down region where ID increases rapidly with small increase of VDS.

We consider that VGS=0. positive voltage VDS is applied to drain w.r.t source. As VDS increases, width of the depletion region remains very small and semiconductor bar behaves as a simple resistor. So, ID increase almost linearly with VDS.

As VDS is kept on increasing, the depletion region intrudes into the channel more toward the drain. As VDS continues to increase the channel opening near drain shrinks and channel resistance increases further. At some value of VDS the depletion regions meet near the drain to pinch off the channel. This value of VDS is the saturation voltage VDSat. The differentiation channel resistance is very high in the saturation region.

For a large value of VDS, the reverse voltage between the channel and gate becomes sufficient to cause breakdown of the gate junction, resulting in asharp reverse of drain current