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Design synchronous counter to count the sequence 0-1-2-3-4-5-0.
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Answer:

JK flip-flop:-

  • The uncertainity in the state of SR flipflop when S=R=1 can be eliminated in JK flip-flop.The logic symbol and truth table of JK flipflop are given below.

Counter:-

  • A counter is a register capable of counting the number of clock pulses arriving at the clock input. The n-bit counter has n flipflops and it has 2n distinct states.

Mod-6 Synchronous Counter:- 

  • In synchronous counter are clocked simultaneously, so the speed of operation improves significantly. Mod counter with less than 2n states can be constructed by allowing the counter to skip states that are not required. Mod-6 synchronous counter can count from 000 to 101 and on next clock pulse it returns back to initial state i.e. 000.

Design of synchronous mod-6 counter using clocked JK flip-flops.

  1. Find the number of flip flops for the required MOD counter.
  2. Choose the type of flipflops to be used.
  3. Write the exitation table of the selected flip flop.
  4. Draw the state diagram.
  5. Determine the flipflop inputs which must be present for the desired next state from the present state using the exitation table of the selected flip flop.
  6. Prepare k-map for each flip-flop input in terms of flip-flop outputs.Simplify the K-map and obtain the minimal expression.
  7. Connect the circuit using flipflops and other gates corresponding to the minimized expression.

Step 1: Find the number of flip flops for the required MOD counter.

  • As we have to construct Mod-6 counter i.e N = 6.
  • Number of flipflops required can be caluculated for minimum value of n which satisfies the below equation
  • $2^n \ge N$
  • As N=6 then n=3.
  • Thus Number of flipflops required = 3

Step 2: Choose the type of flipflops to be used.

  • As we have to design Mod-6 counter so let us select JK flipflop.

Step 3: Write the exitation table of the selected flip flop.

Step 4: Draw the state diagram of required Mod counter.

  • The states of a Mod-6 counter can be represented by a state diagram. Each counter state in the state diagram is represented by a circle containg a binary value. The prograssion is shown by a series of directional arrows.

Step 5: Determine the flipflop inputs which must be present for the desired next state from the present state using the exitation  table of the selected flip flop.

Present state Next State Synchronous Inputs
QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X

Step 6:Prepare k-map for each flip-flop input in terms of flip-flop outputs.Simplify the K-map and obtain the minimal expression.

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