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Write VHDL code for 3-bit up counter
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written 4.5 years ago by
teamques10
★ 70k
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity COUNTER is
Port ( clk: in STD_LOGIC;
output : out STD_LOGIC_VECTOR (2 downto 0));
end COUNTER;
architecture PROGRAM of COUNTER is
signal count : std_logic_vector (2 downto 0) := "000";
begin
process(clk)
begin
if (clk'event and clk = '1') then
count <= count …
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