Full adder using behavioural description in VHDL,

library IEEE;

use IEEE.STD_LOGIC-1164.ALL;

entity fulladder is

port (a, b, ci: in std_logic; sum, co: out std_logic);

end fulladder;

entity fa of fulladder is

begin

process(ci)

begin

if (ci == 0)

sum <= a xor b;

co <= a and b;

else

sum <= a xnor b;

co <= a or b;

end if;

end process:

end fa;