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Design a 2 bit synchronous up/down counter usign T-flops
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written 4.6 years ago by
teamques10
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Synchronous up/down counter counts in both ways from 00 to 1 and from 11 to 00. Since, the counter is synchronous, the same clock pulse is given to all T-flipflops.
2-bit synchronous up/down counter
The circuit has an up control input and a down control input.
When the up input is '1', the circuit counts up, since the T inputs recieve their signals from the values of previous normal outputs of the flipflops.
Truth Table:
| Selection lines | Inputs | ||||
|---|---|---|---|---|---|
| A | B | C | D | F | |
| 0 | 0 | 0 | 0 | 1 | $\begin{align*}F&=C’D’+CD’\\[2ex] &=D’[C+C’]\\[2ex] F&=D’\end{align*}$ |
| 0 | 0 | 0 | 1 | 0 | |
| 0 | 0 | 1 | 0 | 1 | |
| 0 | 0 | 1 | 1 | 0 | |
| 0 | 1 | 0 | 0 | 1 | $\begin{align*}F&=C’D’+C’D+CD\\[2ex] &=C’D’+D[C+C’]\\[2ex] &=(D+D’)(D+C’)\\[2ex] F&=(C’+D)\end{align*}$ |
| 0 | 1 | 0 | 1 | 1 | |
| 0 | 1 | 1 | 0 | 0 | |
| 0 | 1 | 1 | 1 | 1 | |
| 1 | 0 | 0 | 0 | 1 | $\begin{align*}F&=C’D’+C’D+CD\\[2ex] F&=C’+D\end{align*}$ |
| 1 | 0 | 0 | 1 | 1 | |
| 1 | 0 | 1 | 0 | 0 | |
| 1 | 0 | 1 | 1 | 1 | |
| 1 | 1 | 0 | 0 | 0 | $F=CD’$ |
| 1 | 1 | 0 | 1 | 0 | |
| 1 | 1 | 1 | 0 | 1 | |
| 1 | 1 | 1 | 1 | 0 |
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