If the register has both shifting the bits and parallel load capabilities, it is referred as Universal shift register.

Function table:

Mode Control:

A clear control to clear the register to 0.

A clock input to synchronize the operations.

A shift right control to enable the shift right operation and the serial input and output lines associated with the shift right.

A shift left control to enable the shift left operation and the serial input and output lines associated with the shift left.

A parallel load control to enable a parallel transfer and the n input lines associated with the parallel transfer.

Working:

The 4-bit Universal shift register consists of four D-flipflops and four multiplexers.

The four mux have two common selection inputs S1 and S0.

When S1S0=00, Input '0' in each mux is selected. The present value of the register is applied to the D inputs of the flipflops. This condition forms a path from the output of each flipflop into the input of the same flipflop.

When S1S0=01, Input '1' in each mux is selected. Terminal 1 of the mux inputs has a path to the D inputs of the flipflops. This causes a shift right operation, with the serial input transferred into flipflop A4.

When S1S0=10, a shift left operation results, with the other serial input going into flipflop A1.

When S1S0=11, the binary information on the parallel input lines is transferred into the register simultaneously during the next clock edge.