written 3.8 years ago by |
Master Slave JK flipflop is a cascade of two S-R flipflop with feedback from the output of second to input of first.
Circuit Diagram:
Master is a positive level triggered, but due to the presence of the inverter in the clock line, the slave will respond to the negative level.
Hence, when the clock=1 (positive level) the master is active and the slave is inactive.
When the clock=0, the slave is active and the master is inactive.
Truth Table:
Inputs | Outputs | State | |||
---|---|---|---|---|---|
E | J | K | Qn+1 | Qn+1 | |
1 | 0 | 0 | Qn | Qn' | No change |
1 | 0 | 1 | 0 | 1 | Reset |
1 | 1 | 0 | 1 | 0 | Set |
1 | 1 | 1 | Qn' | Qn | Toggle |
Operation:
Case-1:
When J=K=0 (No change)
When clock=0, the slave becomes active and master is inactive. But since the S and R inputs have not changed, the slave outputs will also remain unchanged.
Therefore, the output will not change if J=K=0.
Case-2:
When J=0 and K=1 (Reset)
When clock=1; Master is active, Slave inactive. Therefore, output of master becomes Q1=0 and Q1'=1. Therefore, S=0 and R=1.
When clock=0; Slave active, Master inactive. Therefore, output of the slave becomes Q=0 and Q'=1.
Again clock=1; Master active, Slave inactive. Therefore, even with the changed outputs Q=0 and Q'=1; fed back to the master, then its output will be Q1=0 and Q1'=1. Therefore, S=0 and R=1. Thus we get a stable output from the Master Slave.
Case-3:
When J=1 and K=0 (Set)
When clock=1; Master active, Slave inactive,
Therefore, outputs of the master become Q1=1 and Q1'=0
That means S=1 and R=0
When clock=0; Slave active, Master inactive.
Therefore, output of the slave become Q=1 and Q'=0
Again clock=1; then it can be shown that the outputs of the slave are stabilized to Q=1 and Q'-0.
Case-4:
When J=K=1 (Toggle)
When clock=1; Master active and slave inactive, output of master will toggle. So S and R also will be inverted.
Clock=0; Slave active and master inactive. The outputs of the slave will toggle.
Therefore, these changed outputs are returned back to the master inputs. But since clock=0, the master is still inactive. So it doesn't respond to these changed outputs. This avoids multiple toggling which leads to race around condition.
The master slave flipflop will avoid the race around condition.