Ripple counters are also known as asynchronous counters because each flipflop is triggered by the output of the previous flipflop.

• A ripple counter with n flipflops can have 2n states
• The clock pulse which we give externally is fed into flipflop and is rippled or moved throough the other counters after some propagation delays, like ripplr on the water, hence the name ripple counter.

3-bit Up Down Counter

• The inputs of the flipflop has set to high
• Based on the control signals UP and DOWN, the counter performs its operation

Case-1:

If UP=1 and DOWN=0, then

the NAND network between FF0 and FF1 will give the non-inverted output "Q" of FF0 as the clock input of FF1.

Similarly, the output Q of FF1 will be given through other NAND network into the clock input of FF2. Thus the counter will count "UP".

Case-2:

If UP=0 and DOWN=1, then

the inverted outputs of FF0 and FF1 (i.e. Q' and Q1') are given as the clock inputs of FF1 and FF2 respectively.

If the flipflops are originally reset to zeros, then the counter will count downwards as input pulses are applied.

Table:

Note:

• An UP counter using n flifpflops counts upward from a minimum count i.e. from 0 to 2n-1
• A DOWN counter using n flipflops counts downwards from a maximum of 2n-1 to 0