Draw standard TTL 2 input NAND gate circuit, discuss its operation and draw its transfer characteristics

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written 4.6 years ago by

teamques10 ★ 70k

modified 3.5 years ago by

phenjoisilab • 0

The 2-input TTL NAND gate circuit operation is understood by dividing into three parts-

Diode AND gates and input protection
Phase splitter
Output stage

Functional Table: Of a TTL 2-input NAND

X	Y	VA	Q2	Q3	Q4	Q5	Q6	VZ	Z
L	L	≤1.05	off	on	on	off	off	2.7	H
L	H	≤1.05	off	on	on	off	off	2.7	H
H	L	≤1.05	off	on	on	off	off	2.7	H
H	H	1.2	on	off	off	on	on	≤0.35	L

Truth Table:

X	Y	Z
0	0	1
0	1	1
1	0	1
0	0	0

Logic Symbol:

Operation:

Diodes D1X and D1Y and resistor R1 form an AND gate. Clamp diodes D2X and D2Y limit undesirable negative excursions on the inputs to a single diode drop.

Transistor Q2 and the surrounding resistors form a phase splitter that controls the output stage. Depending on whether the AND gate produces a "low" or a "high" voltage at VA, Q2 is either turned on or cut off.

The output stage has two transistors, Q4 and Q5, only one of which is on at any time. The TTL output stage is sometimes called a totem-pole or push-pull output. Similar to the p-channel and n-channel transistors in CMOS, Q4 and Q5 provide active pull-up and pull-down to the "high" and "low" states respecively.

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