Compare and explain different types of ADCs

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Parameters	Dual Slope ADC	Flash ADC	SAR ADC	Sigma-delta
Resolution	High	Low	Medium	High
Cost	Medium	High	Low	Low
Accuracy	High	Low	Medium	Low
Speed	Slow	Very Fast	Medium-Fast	Slow
Resolution (Bits)	12-18	4-12	8-16	12-24
Disadvantages	Slow Conversion rate. High precision external components required to achieve accuracy.	High power Consumption, large size	Speed Limited to 5Msps	Slow due to oversampling
Conversion Time	Conversion time doubles with every bit increase in resolution.	Conversion Time does not change with increased resolution.	Increases linearly with increased resolution.	Trade-off between data output rate and noise free resolution.
Encoding Method	Analog Integration	Thermometer Code Encoding	Successive Approximation	Over-Sampling Modulator, Digital Decimation Filter

PARALLEL OR FLASH ADC :

1) The circuit diagram is shown below.

2) It consists of a resistive divider network,8 op-amp comparator and * line to 3 line encoder.

3) The non-inverting terminal of each comparator is connected to analog input voltage VA

4) The inverting terminal of each comparator is connected to a different reference voltage.

5) An each comparator compares the analog input voltage iVA with corresponding reference voltage of that comparator.

6)The outputs of these comparators are given to the encoder.

7) This encoder will produce 3-bit digital output:

Input Voltage	Output of Comparator	Output of priority encoder
VA	X7	X6	X5	X4	X3	X2	X1	X0	Y2	Y1	Y0
0 to VR/8	0	0	0	0	0	0	0	1	0	0	0
VR/8 to VR/4	0	0	0	0	0	0	1	1	0	0	1
VR/4 to 3 VR/8	0	0	0	0	0	1	1	1	0	1	0
3 VR/8 to VR/2	0	0	0	0	1	1	1	1	0	1	1
VR/2 to 5 VR/8	0	0	0	1	1	1	1	1	1	0	0
5 VR/8 to
3 VR/4	0	0	1	1	1	1	1	1	1	0	1
3 VR/4 to
7 VR/8	0	1	1	1	1	1	1	1	1	1	0
7 VR/8 to VR	1	1	1	1	1	1	1	1	1	1	1

COUNTER TYPE ADC:-

1) The circuit diagram is shown below.

2) In this type, DACs input code is adjusted until DACs output comes with ± (1/2) LSB to the canalog input which is to be converted to binary digital form.

3) The circuit consists of DAC, comparator, Binary counter and AND gate.

4) The analog input voltage which is required to convert into digital is given to non-inverting terminal of comparator.

5) Initially, binary counter is reset to zero count by reset pulse. Upon the release of RESET, the clock pulses can be counted by binary counter.

SUCCESSIVE APPROXIMATION ADC :

Successive Approximation Analog-to-Digital Converter

Fig. Successive Approximation ADC

In this method of analog-to-digital conversion successive comparisons are made between the input signal and the half of the input range. This input range is reduced in each comparison. The number of comparisons is equal the number of bits of the analog-to-digital converter output.

An example is shows in figure above. An analog input voltage of 6.81 V was converted to a digital value. The processes to do this were comparing the input voltage to the half of the input range (5 V). Then a digital value 1 was attributed to the most significant bit (msb) because the input voltage was lower than the half of the input range.

Then the input range was reduced to its half, and a new comparison was made. The next bit received the digital value 0 because in this comparison the input voltage was bigger than the half of the new input range. These steps were repeated eight times in this case, approximating the digital output value to the analog input voltage value.

DUAL SLOPE INTEGRATOR ADC :

As shown in figure 1, the input voltage ‘Vi’ is integrated with the slope of the integrator output proportional to the test input voltage. After a fixed time equal to t1, the input voltage is disconnected and the integrator input is connected to a negative voltage ‘VR’. The integrator output will have a negative slope which is constant and proportional to the magnitude of the input voltage.

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