Trench capacitor:

A storage cell that uses a trench capacitor is shown in the figure.

The capacitor is created by using a reactive ion etch (RIE) process to create a deep trench in the silicon. The sides are oxidised to create a glass insulator and then doped polysilicon is used to fill the trench and acts as the upper plate. The lower plate is created by an n+ implant along the entire wall area. The increase in plate area AP is achieved by using the sidewalls of the trench without increasing the footprint area Acell.

Stacked capacitor:

A stacked capacitor design places a polysilicon structure on top of the access transistor as portrayed in the figure below.

Advanced 3-dimesional structures can be created to form the uppers and lower plates. The plate area AP depends upon the surface geometry create by the poly plates. Many interesting stacked capacitor designs have been published in the literature. In addition, surface corrugations and bumps have been added to further increase the value of CS.