**1 Answer**

written 3.4 years ago by |

The three geometrical dimensions of an interconnect line that are set in the processing are the width *w*, the thickness *t*, and the oxide thickness *Tox.* Improved lithography allows us to reduce the linewidth to a smaller value

where s>1 is the scaling factor. This is the fundamental effect of scaling the surface geometry of an interconnect line. Because of this line resistance per unit length increases by factor s.

so the resistivity ρ is not changed by shrinking *w*, so that the line resistance per unit length increases as seen by writing,

If we assume that the line length *l* scales according to

then the total line resistance is invariant such that Rline' = Rline.

The capacitance per unit length decreases as the surface dimensions are scaled by noting the reduction in the first term as

which gives

If we ignore the fringing effect then we get

Scaling the line length then approximates the new line capacitance as

which shows 1/s2 as the reduction.

A polysilicon line will exibit the highest sheet resistance in a process even if it is silicided. In this case, it would be important to decrease the line length so as to increase the value of Rline. The time constant for the line scales according to

which is due to the reduction in the line capacitance. A thinner oxide increases c, so that both Rline and Cline would increse, leading to longer delays. If we instead increase *t* and *Tox*, both r and c would be smaller.