Clock skew is where the timing of a clock is out of phase with the system reference. It can be originated from different sources, and limits the clock frequency. In a synchronous system, this is equivalent to limiting the data flow rate and the overall speed.
Clock jitter refers to the temporal variation of the clock period at a given point i.e. the clock period can expand on a cycle-by cycle basis. It is strictly a temporal uncertainty measure and is often specified at a given point on the chip. Jitter directly impacts the performance of a sequential system.
Clock jitter is one of the reasons which lead to clock skew.
Jitter is caused by high-frequency environmental variation, particularly power supply noise. This noise leads to delay variation in the clock buffers and gaters in both time and space. Jitter is particularly insidious because it occurs too rapidly for compensation circuits to be able to counter it. Some engineers do not report jitter as part of the skew. In such a case, they must include both jitter and skew in the setup and hold time budgets.