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Elmore delay is a simple approximation to the delay through an RC network in an electronic system. It is often used in applications such as logic synthesis, delay calculation, static timing analysis, placement and routing, since it is simple to compute and is reasonably accurate. Even where it is not accurate, it is usually faithful, in the sense that reducing the Elmore delay will almost always reduce the true delay, so it is still useful in optimization.

Elmore delay can be thought of in several ways, all mathematically identical.

- For tree structured networks, find the delay through each segment as the R (electrical resistance) times the downstream C (electrical capacitance). Sum the delays from the root to the sink.
- Assume the output is a simple exponential, and find the exponential that has the same integral as the true response. This is also equivalent to moment matching with one moment, since the first moment is a pure exponential.
- Find a one pole approximation to the true frequency response. This is a first-order Padé approximation.

There are many extensions to Elmore delay. It can be extended to upper and lower bounds, to include inductance as well as R and C, to be more accurate (higher order approximations) and so on. See delay calculation for more details and references.

One of the most critical problems in high-density VLSI is dealing with interconnect lines. They produce signal delays that affect system timing, and often lead to extremely complicated layout routing problems.

Silicided poly lines, multiple metal interconnect layers and the use of coppers are some of the examples of the special treatment given to interconnect lines.

The initial part of the analysis is the simplest isolated interconnect line as shown in the figure that represents an arbitrary material layer on the chip.

The dimensions of the line are shown as having a length *l,* a width *w*, and a thickness *t*. The line resistance Rline from In to Out is given by the formula,

$R_{line} = R_s \left( \dfrac{l}{\omega}\right)\Omega $

Where Rs is the sheet resistance of the layer and (*l/w)* is the number of squares with dimensions

(ω x ω) Defining the resistance per unit length r by

$r = \dfrac{R_s}{\omega}\Omega/cm$

the equation becomes

$R_{line} = rl$

This shows the increase of parasitic resistance with line length *l* in a form that is easy to deal with. It is obvious that high-resistivity layers such as polysilicon are more problematic that low resistivity metals.

The total lines capacitance *Cline* can be estimated using the simple parallel-plate formula

$C_{line}=\dfrac{\epsilon_{ o \ x} l\omega}{T_{o x}}F$

where is the thickness of the insulating oxide between the line and the substrate. is also called self-capacitance of the line.

An empirical equation for the capacitance per unit length *c* that accounts for fringing electric fields from the edges and sides when the line is at a positive voltage is

$c= \epsilon_{o \ x} \left[ 1.15\left( \dfrac{\omega}{T_{o \ x}} \right) + 2.8\left(\dfrac{t}{T_{o \ x}}\right)^{0.222} \right] F/cm$

Such that is the total capacitance in farads.

*RC Effect*

The simplest approach to modeling the line is to construct the simple two-element circuit shown in the figure to include the effects of the line from In to Out. This is called *single-rung ladder cirucit* because of the way it is drawn. If the voltage input vi(t) changes from o to a in a step-like manner, the change in the output voltage v0(t) is delayed by the time constant

$\tau = R_{line}C_{line}$

which constitutes a low-order estimate of how the interconnect line affects the signal transmission.

In the following figure, the input voltage vi(t) is applied at z=0 while the output is at z=*l*. If we pulse the input voltage to vi → VDD , then the driving source must move current through the resistive line while simultaneously charging the line capacitance it encounters.

Physically, the charging starts at z=0 and progresses to the right with increasing z, so that the line voltage itself is really a function of both position z and time t. Hence, it’s designated as *v* (*z,t*) . Both resistance and capacitance of the line are incremental in nature; approximating their values using the lumped element values *R**line* and *Cline* inherently limits the accuracy of the analysis. The line resistance and capacitance are divided into m-segments with values given by

$R_m = \dfrac{R_{line}}{m} \ and \ \ C_m = \dfrac{C_{line}}{m}$

When m=1, the circuit is defined by the refernece time constant

$\tau = R_1C_1 \\[2ex] \tau = R_{line}C_{line}$

When m=2, the time constant is

$\tau = C_2(2R_2)+C_2(R_2)\\[2ex] \tau = 3R_2C_2$

And the time constatnt for a 3-rung ladder will be

$\tau = C_3(3R_2)+C_3(2R_3)+C_3(R_3) = 6R_3C_3$

In general, time constant of an m-rung ladder is

$\tau_m =\dfrac{m(m+1)}{2}R_mC_m$

Substituting *Rm* and *Cm* , we get,

$\tau_m = \dfrac{m(m+1)}{2}\left( \dfrac{R_{line}}{m} \right) \left( \dfrac{C_{line}}{m} \right)\\[2ex] \tau_m = \dfrac{m(m+1)}{2m^2}R_{line}C_{line}$

For large values of m,

$\tau = \tau_m \rightarrow \dfrac{1}{2}R_{line}C_{line}$